Lines Matching refs:io_base
45 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_mask_and_ack() local
48 clrbits32(io_base + HW_BROADWAY_IMR, mask); in hlwd_pic_mask_and_ack()
49 out_be32(io_base + HW_BROADWAY_ICR, mask); in hlwd_pic_mask_and_ack()
55 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_ack() local
57 out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); in hlwd_pic_ack()
63 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_mask() local
65 clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); in hlwd_pic_mask()
71 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_unmask() local
73 setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); in hlwd_pic_unmask()
76 clrbits32(io_base + HW_STARLET_IMR, 1 << irq); in hlwd_pic_unmask()
110 void __iomem *io_base = h->host_data; in __hlwd_pic_get_irq() local
113 irq_status = in_be32(io_base + HW_BROADWAY_ICR) & in __hlwd_pic_get_irq()
114 in_be32(io_base + HW_BROADWAY_IMR); in __hlwd_pic_get_irq()
149 static void __hlwd_quiesce(void __iomem *io_base) in __hlwd_quiesce() argument
152 out_be32(io_base + HW_BROADWAY_IMR, 0); in __hlwd_quiesce()
153 out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff); in __hlwd_quiesce()
160 void __iomem *io_base; in hlwd_pic_init() local
168 io_base = ioremap(res.start, resource_size(&res)); in hlwd_pic_init()
169 if (!io_base) { in hlwd_pic_init()
174 pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); in hlwd_pic_init()
176 __hlwd_quiesce(io_base); in hlwd_pic_init()
179 &hlwd_irq_domain_ops, io_base); in hlwd_pic_init()
182 iounmap(io_base); in hlwd_pic_init()
230 void __iomem *io_base = hlwd_irq_host->host_data; in hlwd_quiesce() local
232 __hlwd_quiesce(io_base); in hlwd_quiesce()