Lines Matching refs:hose
139 struct pci_controller *hose; in macrisc_cfg_map_bus() local
141 hose = pci_bus_to_host(bus); in macrisc_cfg_map_bus()
142 if (hose == NULL) in macrisc_cfg_map_bus()
145 if (bus->number == hose->first_busno) { in macrisc_cfg_map_bus()
154 out_le32(hose->cfg_addr, caddr); in macrisc_cfg_map_bus()
155 } while (in_le32(hose->cfg_addr) != caddr); in macrisc_cfg_map_bus()
158 return hose->cfg_data + offset; in macrisc_cfg_map_bus()
203 static void __init setup_chaos(struct pci_controller *hose, in setup_chaos() argument
207 hose->ops = &chaos_pci_ops; in setup_chaos()
208 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); in setup_chaos()
209 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); in setup_chaos()
228 static int u3_ht_skip_device(struct pci_controller *hose, in u3_ht_skip_device() argument
244 busdn = hose->dn; in u3_ht_skip_device()
269 static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus, in u3_ht_cfg_access() argument
273 if (bus == hose->first_busno) { in u3_ht_cfg_access()
275 return hose->cfg_data + U3_HT_CFA0(devfn, offset); in u3_ht_cfg_access()
277 return ((void __iomem *)hose->cfg_addr) + (offset << 2); in u3_ht_cfg_access()
279 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); in u3_ht_cfg_access()
285 struct pci_controller *hose; in u3_ht_read_config() local
289 hose = pci_bus_to_host(bus); in u3_ht_read_config()
290 if (hose == NULL) in u3_ht_read_config()
294 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); in u3_ht_read_config()
298 switch (u3_ht_skip_device(hose, bus, devfn)) { in u3_ht_read_config()
336 struct pci_controller *hose; in u3_ht_write_config() local
340 hose = pci_bus_to_host(bus); in u3_ht_write_config()
341 if (hose == NULL) in u3_ht_write_config()
345 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); in u3_ht_write_config()
349 switch (u3_ht_skip_device(hose, bus, devfn)) { in u3_ht_write_config()
399 struct pci_controller *hose; in u4_pcie_cfg_map_bus() local
405 hose = pci_bus_to_host(bus); in u4_pcie_cfg_map_bus()
406 if (!hose) in u4_pcie_cfg_map_bus()
409 if (bus->number == hose->first_busno) { in u4_pcie_cfg_map_bus()
416 out_le32(hose->cfg_addr, caddr); in u4_pcie_cfg_map_bus()
417 } while (in_le32(hose->cfg_addr) != caddr); in u4_pcie_cfg_map_bus()
420 return hose->cfg_data + offset; in u4_pcie_cfg_map_bus()
493 struct pci_controller* hose; in init_p2pbridge() local
509 hose = pci_find_hose_for_OF_device(p2pbridge); in init_p2pbridge()
510 if (!hose) { in init_p2pbridge()
514 if (early_read_config_word(hose, bus, devfn, in init_p2pbridge()
521 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); in init_p2pbridge()
539 struct pci_controller* hose = in init_second_ohare() local
541 if (!hose) { in init_second_ohare()
546 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); in init_second_ohare()
549 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); in init_second_ohare()
566 struct pci_controller *hose; in fixup_nec_usb2() local
588 hose = pci_find_hose_for_OF_device(nec); in fixup_nec_usb2()
589 if (!hose) in fixup_nec_usb2()
591 early_read_config_dword(hose, bus, devfn, 0xe4, &data); in fixup_nec_usb2()
596 early_write_config_dword(hose, bus, devfn, 0xe4, data); in fixup_nec_usb2()
601 static void __init setup_bandit(struct pci_controller *hose, in setup_bandit() argument
604 hose->ops = ¯isc_pci_ops; in setup_bandit()
605 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); in setup_bandit()
606 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); in setup_bandit()
607 init_bandit(hose); in setup_bandit()
610 static int __init setup_uninorth(struct pci_controller *hose, in setup_uninorth() argument
615 hose->ops = ¯isc_pci_ops; in setup_uninorth()
616 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); in setup_uninorth()
617 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); in setup_uninorth()
624 static void __init setup_u3_agp(struct pci_controller* hose) in setup_u3_agp() argument
635 hose->first_busno = 0xf0; in setup_u3_agp()
636 hose->last_busno = 0xff; in setup_u3_agp()
638 hose->ops = ¯isc_pci_ops; in setup_u3_agp()
639 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); in setup_u3_agp()
640 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); in setup_u3_agp()
641 u3_agp = hose; in setup_u3_agp()
644 static void __init setup_u4_pcie(struct pci_controller* hose) in setup_u4_pcie() argument
649 hose->ops = &u4_pcie_pci_ops; in setup_u4_pcie()
650 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); in setup_u4_pcie()
651 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); in setup_u4_pcie()
659 hose->first_busno = 0x00; in setup_u4_pcie()
660 hose->last_busno = 0xff; in setup_u4_pcie()
663 static void __init parse_region_decode(struct pci_controller *hose, in parse_region_decode() argument
687 hose->mem_resources[cur].flags = IORESOURCE_MEM; in parse_region_decode()
688 hose->mem_resources[cur].name = hose->dn->full_name; in parse_region_decode()
689 hose->mem_resources[cur].start = base; in parse_region_decode()
690 hose->mem_resources[cur].end = end; in parse_region_decode()
691 hose->mem_offset[cur] = 0; in parse_region_decode()
695 hose->mem_resources[cur].end = end; in parse_region_decode()
701 static void __init setup_u3_ht(struct pci_controller* hose) in setup_u3_ht() argument
703 struct device_node *np = hose->dn; in setup_u3_ht()
707 hose->ops = &u3_ht_pci_ops; in setup_u3_ht()
720 hose->cfg_data = ioremap(cfg_res.start, 0x02000000); in setup_u3_ht()
721 hose->cfg_addr = ioremap(self_res.start, resource_size(&self_res)); in setup_u3_ht()
728 hose->io_base_phys = 0xf4000000; in setup_u3_ht()
729 hose->pci_io_size = 0x00400000; in setup_u3_ht()
730 hose->io_resource.name = np->full_name; in setup_u3_ht()
731 hose->io_resource.start = 0; in setup_u3_ht()
732 hose->io_resource.end = 0x003fffff; in setup_u3_ht()
733 hose->io_resource.flags = IORESOURCE_IO; in setup_u3_ht()
734 hose->first_busno = 0; in setup_u3_ht()
735 hose->last_busno = 0xef; in setup_u3_ht()
738 decode = in_be32(hose->cfg_addr + 0x80); in setup_u3_ht()
762 parse_region_decode(hose, decode); in setup_u3_ht()
774 struct pci_controller *hose; in pmac_add_bridge() local
792 hose = pcibios_alloc_controller(dev); in pmac_add_bridge()
793 if (!hose) in pmac_add_bridge()
795 hose->first_busno = bus_range ? bus_range[0] : 0; in pmac_add_bridge()
796 hose->last_busno = bus_range ? bus_range[1] : 0xff; in pmac_add_bridge()
797 hose->controller_ops = pmac_pci_controller_ops; in pmac_add_bridge()
804 setup_u3_agp(hose); in pmac_add_bridge()
808 setup_u3_ht(hose); in pmac_add_bridge()
812 setup_u4_pcie(hose); in pmac_add_bridge()
817 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); in pmac_add_bridge()
823 primary = setup_uninorth(hose, &rsrc); in pmac_add_bridge()
827 setup_grackle(hose); in pmac_add_bridge()
830 setup_bandit(hose, &rsrc); in pmac_add_bridge()
833 setup_chaos(hose, &rsrc); in pmac_add_bridge()
839 disp_name, (unsigned long long)rsrc.start, hose->first_busno, in pmac_add_bridge()
840 hose->last_busno); in pmac_add_bridge()
844 hose, hose->cfg_addr, hose->cfg_data); in pmac_add_bridge()
848 pci_process_bridge_OF_ranges(hose, dev, primary); in pmac_add_bridge()
855 pci_devs_phb_init_dynamic(hose); in pmac_add_bridge()
882 struct pci_controller *hose = pci_bus_to_host(bridge->bus); in pmac_pci_root_bridge_prepare() local
885 if (hose != u3_agp) in pmac_pci_root_bridge_prepare()
893 np = hose->dn; in pmac_pci_root_bridge_prepare()