Lines Matching refs:TGT
80 #define TGT 256 macro
127 } else if (bus == TGT) { in grpci1_cfg_r32()
145 grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, tmp); in grpci1_cfg_r32()
190 } else if (bus == TGT) { in grpci1_cfg_w32()
442 grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, 0xffffffff); in grpci1_hw_init()
443 grpci1_cfg_r32(priv, TGT, 0, PCI_BASE_ADDRESS_0, &bar_sz); in grpci1_hw_init()
446 grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, pciadr); in grpci1_hw_init()
452 grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_1, ahbadr); in grpci1_hw_init()
459 grpci1_cfg_w8(priv, TGT, 0, PCI_CACHE_LINE_SIZE, 0xff); in grpci1_hw_init()
460 grpci1_cfg_w8(priv, TGT, 0, PCI_LATENCY_TIMER, 0x40); in grpci1_hw_init()
463 grpci1_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data); in grpci1_hw_init()
465 grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, data); in grpci1_hw_init()
481 grpci1_cfg_r16(priv, TGT, 0, PCI_STATUS, &status); in grpci1_err_interrupt()
506 grpci1_cfg_w16(priv, TGT, 0, PCI_STATUS, status); in grpci1_err_interrupt()