Lines Matching refs:C
147 #define C(x) PERF_COUNT_HW_CACHE_##x macro
221 [C(L1D)] = {
222 [C(OP_READ)] = {
223 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
224 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
226 [C(OP_WRITE)] = {
227 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
228 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
230 [C(OP_PREFETCH)] = {
231 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
232 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
235 [C(L1I)] = {
236 [C(OP_READ)] = {
237 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
238 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
240 [ C(OP_WRITE) ] = {
241 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
242 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
244 [ C(OP_PREFETCH) ] = {
245 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
246 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
249 [C(LL)] = {
250 [C(OP_READ)] = {
251 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
252 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
254 [C(OP_WRITE)] = {
255 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
256 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
258 [C(OP_PREFETCH)] = {
259 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
260 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
263 [C(DTLB)] = {
264 [C(OP_READ)] = {
265 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
266 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
268 [ C(OP_WRITE) ] = {
269 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
270 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
272 [ C(OP_PREFETCH) ] = {
273 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
274 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
277 [C(ITLB)] = {
278 [C(OP_READ)] = {
279 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
280 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
282 [ C(OP_WRITE) ] = {
283 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
284 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
286 [ C(OP_PREFETCH) ] = {
287 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
288 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
291 [C(BPU)] = {
292 [C(OP_READ)] = {
293 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
294 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
296 [ C(OP_WRITE) ] = {
297 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
298 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
300 [ C(OP_PREFETCH) ] = {
301 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
302 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
305 [C(NODE)] = {
306 [C(OP_READ)] = {
307 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
308 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
310 [ C(OP_WRITE) ] = {
311 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
312 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
314 [ C(OP_PREFETCH) ] = {
315 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
316 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
359 [C(L1D)] = {
360 [C(OP_READ)] = {
361 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
362 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
364 [C(OP_WRITE)] = {
365 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
366 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
368 [C(OP_PREFETCH)] = {
369 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
370 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
373 [C(L1I)] = {
374 [C(OP_READ)] = {
375 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
376 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
378 [ C(OP_WRITE) ] = {
379 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
380 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
382 [ C(OP_PREFETCH) ] = {
383 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
384 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
387 [C(LL)] = {
388 [C(OP_READ)] = {
389 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
390 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
392 [C(OP_WRITE)] = {
393 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
394 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
396 [C(OP_PREFETCH)] = {
397 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
398 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
401 [C(DTLB)] = {
402 [C(OP_READ)] = {
403 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
404 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
406 [ C(OP_WRITE) ] = {
407 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
408 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
410 [ C(OP_PREFETCH) ] = {
411 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
412 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
415 [C(ITLB)] = {
416 [C(OP_READ)] = {
417 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
418 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
420 [ C(OP_WRITE) ] = {
421 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
422 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
424 [ C(OP_PREFETCH) ] = {
425 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
426 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
429 [C(BPU)] = {
430 [C(OP_READ)] = {
431 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
432 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
434 [ C(OP_WRITE) ] = {
435 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
436 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
438 [ C(OP_PREFETCH) ] = {
439 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
440 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
443 [C(NODE)] = {
444 [C(OP_READ)] = {
445 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
446 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
448 [ C(OP_WRITE) ] = {
449 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
450 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
452 [ C(OP_PREFETCH) ] = {
453 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
454 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
494 [C(L1D)] = {
495 [C(OP_READ)] = {
496 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
497 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
499 [C(OP_WRITE)] = {
500 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
501 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
503 [C(OP_PREFETCH)] = {
504 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
505 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
508 [C(L1I)] = {
509 [C(OP_READ)] = {
510 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
511 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
513 [ C(OP_WRITE) ] = {
514 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
515 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
517 [ C(OP_PREFETCH) ] = {
518 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
519 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
522 [C(LL)] = {
523 [C(OP_READ)] = {
524 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
525 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
527 [C(OP_WRITE)] = {
528 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
529 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
531 [C(OP_PREFETCH)] = {
532 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
533 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
536 [C(DTLB)] = {
537 [C(OP_READ)] = {
538 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
539 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
541 [ C(OP_WRITE) ] = {
542 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
543 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
545 [ C(OP_PREFETCH) ] = {
546 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
547 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
550 [C(ITLB)] = {
551 [C(OP_READ)] = {
552 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
553 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
555 [ C(OP_WRITE) ] = {
556 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
557 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
559 [ C(OP_PREFETCH) ] = {
560 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
561 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
564 [C(BPU)] = {
565 [C(OP_READ)] = {
566 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
567 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
569 [ C(OP_WRITE) ] = {
570 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
571 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
573 [ C(OP_PREFETCH) ] = {
574 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
575 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
578 [C(NODE)] = {
579 [C(OP_READ)] = {
580 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
581 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
583 [ C(OP_WRITE) ] = {
584 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
585 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
587 [ C(OP_PREFETCH) ] = {
588 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
589 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
631 [C(L1D)] = {
632 [C(OP_READ)] = {
633 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
634 [C(RESULT_MISS)] = { (16 << 6) | 0x07 },
636 [C(OP_WRITE)] = {
637 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
638 [C(RESULT_MISS)] = { (16 << 6) | 0x07 },
640 [C(OP_PREFETCH)] = {
641 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
642 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
645 [C(L1I)] = {
646 [C(OP_READ)] = {
647 [C(RESULT_ACCESS)] = { (3 << 6) | 0x3f },
648 [C(RESULT_MISS)] = { (11 << 6) | 0x03 },
650 [ C(OP_WRITE) ] = {
651 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
652 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
654 [ C(OP_PREFETCH) ] = {
655 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
656 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
659 [C(LL)] = {
660 [C(OP_READ)] = {
661 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
662 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
664 [C(OP_WRITE)] = {
665 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
666 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
668 [C(OP_PREFETCH)] = {
669 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
670 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
673 [C(DTLB)] = {
674 [C(OP_READ)] = {
675 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
676 [C(RESULT_MISS)] = { (17 << 6) | 0x3f },
678 [ C(OP_WRITE) ] = {
679 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
680 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
682 [ C(OP_PREFETCH) ] = {
683 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
684 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
687 [C(ITLB)] = {
688 [C(OP_READ)] = {
689 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
690 [C(RESULT_MISS)] = { (6 << 6) | 0x3f },
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
694 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
698 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
701 [C(BPU)] = {
702 [C(OP_READ)] = {
703 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
704 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
708 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
712 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
715 [C(NODE)] = {
716 [C(OP_READ)] = {
717 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
718 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
720 [ C(OP_WRITE) ] = {
721 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
722 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
724 [ C(OP_PREFETCH) ] = {
725 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
726 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },