Lines Matching refs:t0
50 #define roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2, t3, t4, t5, t6, \ argument
57 vmovdqa .Lpre_tf_lo_s1, t0; \
73 filter_8bit(x0, t0, t1, t7, t6); \
74 filter_8bit(x7, t0, t1, t7, t6); \
75 filter_8bit(x1, t0, t1, t7, t6); \
76 filter_8bit(x4, t0, t1, t7, t6); \
77 filter_8bit(x2, t0, t1, t7, t6); \
78 filter_8bit(x5, t0, t1, t7, t6); \
86 vmovdqa .Lpost_tf_lo_s1, t0; \
100 filter_8bit(x0, t0, t1, t7, t6); \
101 filter_8bit(x7, t0, t1, t7, t6); \
102 filter_8bit(x3, t0, t1, t7, t6); \
103 filter_8bit(x6, t0, t1, t7, t6); \
112 vmovq key, t0; \
118 vpsrldq $5, t0, t5; \
119 vpsrldq $1, t0, t1; \
120 vpsrldq $2, t0, t2; \
121 vpsrldq $3, t0, t3; \
122 vpsrldq $4, t0, t4; \
123 vpshufb t6, t0, t0; \
171 vpxor t0, x7, x7; \
268 #define rol32_1_16(v0, v1, v2, v3, t0, t1, t2, zero) \ argument
269 vpcmpgtb v0, zero, t0; \
271 vpabsb t0, t0; \
281 vpor t0, v1, v1; \
283 vpcmpgtb v3, zero, t0; \
285 vpabsb t0, t0; \
289 vpor t0, v0, v0;
298 #define fls16(l, l0, l1, l2, l3, l4, l5, l6, l7, r, t0, t1, t2, t3, tt0, \ argument
306 vmovd kll, t0; \
307 vpshufb tt0, t0, t3; \
308 vpsrldq $1, t0, t0; \
309 vpshufb tt0, t0, t2; \
310 vpsrldq $1, t0, t0; \
311 vpshufb tt0, t0, t1; \
312 vpsrldq $1, t0, t0; \
313 vpshufb tt0, t0, t0; \
315 vpand l0, t0, t0; \
320 rol32_1_16(t3, t2, t1, t0, tt1, tt2, tt3, tt0); \
322 vpxor l4, t0, l4; \
337 vmovd krr, t0; \
338 vpshufb tt0, t0, t3; \
339 vpsrldq $1, t0, t0; \
340 vpshufb tt0, t0, t2; \
341 vpsrldq $1, t0, t0; \
342 vpshufb tt0, t0, t1; \
343 vpsrldq $1, t0, t0; \
344 vpshufb tt0, t0, t0; \
346 vpor 4 * 16(r), t0, t0; \
351 vpxor 0 * 16(r), t0, t0; \
355 vmovdqu t0, 0 * 16(r); \
365 vmovd krl, t0; \
366 vpshufb tt0, t0, t3; \
367 vpsrldq $1, t0, t0; \
368 vpshufb tt0, t0, t2; \
369 vpsrldq $1, t0, t0; \
370 vpshufb tt0, t0, t1; \
371 vpsrldq $1, t0, t0; \
372 vpshufb tt0, t0, t0; \
374 vpand 0 * 16(r), t0, t0; \
379 rol32_1_16(t3, t2, t1, t0, tt1, tt2, tt3, tt0); \
381 vpxor 4 * 16(r), t0, t0; \
385 vmovdqu t0, 4 * 16(r); \
396 vmovd klr, t0; \
397 vpshufb tt0, t0, t3; \
398 vpsrldq $1, t0, t0; \
399 vpshufb tt0, t0, t2; \
400 vpsrldq $1, t0, t0; \
401 vpshufb tt0, t0, t1; \
402 vpsrldq $1, t0, t0; \
403 vpshufb tt0, t0, t0; \
405 vpor l4, t0, t0; \
410 vpxor l0, t0, l0; \