Lines Matching refs:slot
140 static u32 __init find_cap(int bus, int slot, int func, int cap) in find_cap() argument
145 if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & in find_cap()
149 pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); in find_cap()
154 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); in find_cap()
159 pos = read_pci_config_byte(bus, slot, func, in find_cap()
166 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order) in read_agp() argument
175 pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func); in read_agp()
176 apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14); in read_agp()
179 bus, slot, func); in read_agp()
195 aper_low = read_pci_config(bus, slot, func, 0x10); in read_agp()
196 aper_hi = read_pci_config(bus, slot, func, 0x14); in read_agp()
204 bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1, in read_agp()
208 bus, slot, func, 32 << *order, apsizereg); in read_agp()
213 bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1, in read_agp()
236 int bus, slot, func; in search_agp_bridge() local
240 for (slot = 0; slot < 32; slot++) { in search_agp_bridge()
244 class = read_pci_config(bus, slot, func, in search_agp_bridge()
253 cap = find_cap(bus, slot, func, in search_agp_bridge()
258 return read_agp(bus, slot, func, cap, in search_agp_bridge()
263 type = read_pci_config_byte(bus, slot, func, in search_agp_bridge()
301 int i, fix, slot, valid_agp = 0; in early_gart_iommu_check() local
325 for (slot = dev_base; slot < dev_limit; slot++) { in early_gart_iommu_check()
326 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) in early_gart_iommu_check()
329 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); in early_gart_iommu_check()
333 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; in early_gart_iommu_check()
381 for (slot = dev_base; slot < dev_limit; slot++) { in early_gart_iommu_check()
382 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) in early_gart_iommu_check()
385 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); in early_gart_iommu_check()
387 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); in early_gart_iommu_check()
400 int fix, slot, valid_agp = 0; in gart_iommu_hole_init() local
426 for (slot = dev_base; slot < dev_limit; slot++) { in gart_iommu_hole_init()
427 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) in gart_iommu_hole_init()
434 ctl = read_pci_config(bus, slot, 3, in gart_iommu_hole_init()
444 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); in gart_iommu_hole_init()
448 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; in gart_iommu_hole_init()
554 for (slot = dev_base; slot < dev_limit; slot++) { in gart_iommu_hole_init()
555 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) in gart_iommu_hole_init()
558 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); in gart_iommu_hole_init()
559 write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25); in gart_iommu_hole_init()