Lines Matching refs:ZERO
3160 #undef ZERO
3161 #define ZERO(reg) writel(0, port_mmio + (reg)) macro
3169 ZERO(0x028); /* command */ in mv5_reset_hc_port()
3171 ZERO(0x004); /* timer */ in mv5_reset_hc_port()
3172 ZERO(0x008); /* irq err cause */ in mv5_reset_hc_port()
3173 ZERO(0x00c); /* irq err mask */ in mv5_reset_hc_port()
3174 ZERO(0x010); /* rq bah */ in mv5_reset_hc_port()
3175 ZERO(0x014); /* rq inp */ in mv5_reset_hc_port()
3176 ZERO(0x018); /* rq outp */ in mv5_reset_hc_port()
3177 ZERO(0x01c); /* respq bah */ in mv5_reset_hc_port()
3178 ZERO(0x024); /* respq outp */ in mv5_reset_hc_port()
3179 ZERO(0x020); /* respq inp */ in mv5_reset_hc_port()
3180 ZERO(0x02c); /* test control */ in mv5_reset_hc_port()
3183 #undef ZERO
3185 #define ZERO(reg) writel(0, hc_mmio + (reg)) macro
3192 ZERO(0x00c); in mv5_reset_one_hc()
3193 ZERO(0x010); in mv5_reset_one_hc()
3194 ZERO(0x014); in mv5_reset_one_hc()
3195 ZERO(0x018); in mv5_reset_one_hc()
3202 #undef ZERO
3220 #undef ZERO
3221 #define ZERO(reg) writel(0, mmio + (reg)) macro
3231 ZERO(MV_PCI_DISC_TIMER); in mv_reset_pci_bus()
3232 ZERO(MV_PCI_MSI_TRIGGER); in mv_reset_pci_bus()
3234 ZERO(MV_PCI_SERR_MASK); in mv_reset_pci_bus()
3235 ZERO(hpriv->irq_cause_offset); in mv_reset_pci_bus()
3236 ZERO(hpriv->irq_mask_offset); in mv_reset_pci_bus()
3237 ZERO(MV_PCI_ERR_LOW_ADDRESS); in mv_reset_pci_bus()
3238 ZERO(MV_PCI_ERR_HIGH_ADDRESS); in mv_reset_pci_bus()
3239 ZERO(MV_PCI_ERR_ATTRIBUTE); in mv_reset_pci_bus()
3240 ZERO(MV_PCI_ERR_COMMAND); in mv_reset_pci_bus()
3242 #undef ZERO
3442 #undef ZERO
3443 #define ZERO(reg) writel(0, port_mmio + (reg)) macro
3451 ZERO(0x028); /* command */ in mv_soc_reset_hc_port()
3453 ZERO(0x004); /* timer */ in mv_soc_reset_hc_port()
3454 ZERO(0x008); /* irq err cause */ in mv_soc_reset_hc_port()
3455 ZERO(0x00c); /* irq err mask */ in mv_soc_reset_hc_port()
3456 ZERO(0x010); /* rq bah */ in mv_soc_reset_hc_port()
3457 ZERO(0x014); /* rq inp */ in mv_soc_reset_hc_port()
3458 ZERO(0x018); /* rq outp */ in mv_soc_reset_hc_port()
3459 ZERO(0x01c); /* respq bah */ in mv_soc_reset_hc_port()
3460 ZERO(0x024); /* respq outp */ in mv_soc_reset_hc_port()
3461 ZERO(0x020); /* respq inp */ in mv_soc_reset_hc_port()
3462 ZERO(0x02c); /* test control */ in mv_soc_reset_hc_port()
3466 #undef ZERO
3468 #define ZERO(reg) writel(0, hc_mmio + (reg)) macro
3474 ZERO(0x00c); in mv_soc_reset_one_hc()
3475 ZERO(0x010); in mv_soc_reset_one_hc()
3476 ZERO(0x014); in mv_soc_reset_one_hc()
3480 #undef ZERO