Lines Matching refs:intel_private
89 } intel_private; variable
91 #define INTEL_GTT_GEN intel_private.driver->gen
92 #define IS_G33 intel_private.driver->is_g33
93 #define IS_PINEVIEW intel_private.driver->is_pineview
94 #define IS_IRONLAKE intel_private.driver->is_ironlake
95 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
113 if (!pci_map_sg(intel_private.pcidev, in intel_gtt_map_memory()
129 pci_unmap_sg(intel_private.pcidev, sg_list, in intel_gtt_unmap_memory()
182 intel_private.i81x_gtt_table = gtt_table; in i810_setup()
184 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); in i810_setup()
186 intel_private.registers = ioremap(reg_addr, KB(64)); in i810_setup()
187 if (!intel_private.registers) in i810_setup()
191 intel_private.registers+I810_PGETBL_CTL); in i810_setup()
193 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; in i810_setup()
195 if ((readl(intel_private.registers+I810_DRAM_CTL) in i810_setup()
197 dev_info(&intel_private.pcidev->dev, in i810_setup()
199 intel_private.num_dcache_entries = 1024; in i810_setup()
207 writel(0, intel_private.registers+I810_PGETBL_CTL); in i810_cleanup()
208 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); in i810_cleanup()
218 > intel_private.num_dcache_entries) in i810_insert_dcache_entries()
226 intel_private.driver->write_entry(addr, in i810_insert_dcache_entries()
304 if (intel_private.needs_dmar) { in intel_gtt_setup_scratch_page()
305 dma_addr = pci_map_page(intel_private.pcidev, page, 0, in intel_gtt_setup_scratch_page()
307 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) { in intel_gtt_setup_scratch_page()
312 intel_private.scratch_page_dma = dma_addr; in intel_gtt_setup_scratch_page()
314 intel_private.scratch_page_dma = page_to_phys(page); in intel_gtt_setup_scratch_page()
316 intel_private.scratch_page = page; in intel_gtt_setup_scratch_page()
335 writel_relaxed(addr | pte_flags, intel_private.gtt + entry); in i810_write_entry()
349 pci_read_config_word(intel_private.bridge_dev, in intel_gtt_stolen_size()
352 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || in intel_gtt_stolen_size()
353 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { in intel_gtt_stolen_size()
365 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); in intel_gtt_stolen_size()
422 dev_info(&intel_private.bridge_dev->dev, "detected %lluK %s memory\n", in intel_gtt_stolen_size()
425 dev_info(&intel_private.bridge_dev->dev, in intel_gtt_stolen_size()
438 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
440 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
443 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); in i965_adjust_pgetbl_size()
446 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); in i965_adjust_pgetbl_size()
455 pci_read_config_word(intel_private.bridge_dev, in i965_gtt_total_entries()
474 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); in i965_gtt_total_entries()
497 dev_info(&intel_private.pcidev->dev, in i965_gtt_total_entries()
513 return intel_private.gtt_mappable_entries; in intel_gtt_total_entries()
524 pci_read_config_dword(intel_private.bridge_dev, in intel_gtt_mappable_entries()
535 pci_read_config_word(intel_private.bridge_dev, in intel_gtt_mappable_entries()
544 aperture_size = pci_resource_len(intel_private.pcidev, 2); in intel_gtt_mappable_entries()
552 set_pages_wb(intel_private.scratch_page, 1); in intel_gtt_teardown_scratch_page()
553 if (intel_private.needs_dmar) in intel_gtt_teardown_scratch_page()
554 pci_unmap_page(intel_private.pcidev, in intel_gtt_teardown_scratch_page()
555 intel_private.scratch_page_dma, in intel_gtt_teardown_scratch_page()
557 __free_page(intel_private.scratch_page); in intel_gtt_teardown_scratch_page()
562 intel_private.driver->cleanup(); in intel_gtt_cleanup()
564 iounmap(intel_private.gtt); in intel_gtt_cleanup()
565 iounmap(intel_private.registers); in intel_gtt_cleanup()
576 const unsigned short gpu_devid = intel_private.pcidev->device; in needs_ilk_vtd_wa()
609 ret = intel_private.driver->setup(); in intel_gtt_init()
613 intel_private.gtt_mappable_entries = intel_gtt_mappable_entries(); in intel_gtt_init()
614 intel_private.gtt_total_entries = intel_gtt_total_entries(); in intel_gtt_init()
617 intel_private.PGETBL_save = in intel_gtt_init()
618 readl(intel_private.registers+I810_PGETBL_CTL) in intel_gtt_init()
622 intel_private.PGETBL_save |= I810_PGETBL_ENABLED; in intel_gtt_init()
624 dev_info(&intel_private.bridge_dev->dev, in intel_gtt_init()
626 intel_private.gtt_total_entries * 4, in intel_gtt_init()
627 intel_private.gtt_mappable_entries * 4); in intel_gtt_init()
629 gtt_map_size = intel_private.gtt_total_entries * 4; in intel_gtt_init()
631 intel_private.gtt = NULL; in intel_gtt_init()
633 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr, in intel_gtt_init()
635 if (intel_private.gtt == NULL) in intel_gtt_init()
636 intel_private.gtt = ioremap(intel_private.gtt_phys_addr, in intel_gtt_init()
638 if (intel_private.gtt == NULL) { in intel_gtt_init()
639 intel_private.driver->cleanup(); in intel_gtt_init()
640 iounmap(intel_private.registers); in intel_gtt_init()
648 intel_private.stolen_size = intel_gtt_stolen_size(); in intel_gtt_init()
650 intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; in intel_gtt_init()
663 intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar); in intel_gtt_init()
682 aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1); in intel_fake_agp_fetch_size()
724 writel(readl(intel_private.registers+I830_HIC) | (1<<31), in i830_chipset_flush()
725 intel_private.registers+I830_HIC); in i830_chipset_flush()
727 while (readl(intel_private.registers+I830_HIC) & (1<<31)) { in i830_chipset_flush()
743 writel_relaxed(addr | pte_flags, intel_private.gtt + entry); in i830_write_entry()
753 pci_read_config_word(intel_private.bridge_dev, in intel_enable_gtt()
756 pci_write_config_word(intel_private.bridge_dev, in intel_enable_gtt()
759 pci_read_config_word(intel_private.bridge_dev, in intel_enable_gtt()
762 dev_err(&intel_private.pcidev->dev, in intel_enable_gtt()
773 writel(0, intel_private.registers+GFX_FLSH_CNTL); in intel_enable_gtt()
775 reg = intel_private.registers+I810_PGETBL_CTL; in intel_enable_gtt()
776 writel(intel_private.PGETBL_save, reg); in intel_enable_gtt()
778 dev_err(&intel_private.pcidev->dev, in intel_enable_gtt()
780 readl(reg), intel_private.PGETBL_save); in intel_enable_gtt()
785 writel(0, intel_private.registers+GFX_FLSH_CNTL); in intel_enable_gtt()
795 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); in i830_setup()
797 intel_private.registers = ioremap(reg_addr, KB(64)); in i830_setup()
798 if (!intel_private.registers) in i830_setup()
801 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; in i830_setup()
826 intel_private.clear_fake_agp = true; in intel_fake_agp_configure()
827 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; in intel_fake_agp_configure()
850 intel_private.driver->write_entry(addr, pg, flags); in intel_gtt_insert_page()
851 readl(intel_private.gtt + pg); in intel_gtt_insert_page()
852 if (intel_private.driver->chipset_flush) in intel_gtt_insert_page()
853 intel_private.driver->chipset_flush(); in intel_gtt_insert_page()
873 intel_private.driver->write_entry(addr, j, flags); in intel_gtt_insert_sg_entries()
877 readl(intel_private.gtt + j - 1); in intel_gtt_insert_sg_entries()
878 if (intel_private.driver->chipset_flush) in intel_gtt_insert_sg_entries()
879 intel_private.driver->chipset_flush(); in intel_gtt_insert_sg_entries()
893 intel_private.driver->write_entry(addr, in intel_gtt_insert_pages()
904 if (intel_private.clear_fake_agp) { in intel_fake_agp_insert_entries()
905 int start = intel_private.stolen_size / PAGE_SIZE; in intel_fake_agp_insert_entries()
906 int end = intel_private.gtt_mappable_entries; in intel_fake_agp_insert_entries()
908 intel_private.clear_fake_agp = false; in intel_fake_agp_insert_entries()
917 if (pg_start + mem->page_count > intel_private.gtt_total_entries) in intel_fake_agp_insert_entries()
923 if (!intel_private.driver->check_flags(type)) in intel_fake_agp_insert_entries()
929 if (intel_private.needs_dmar) { in intel_fake_agp_insert_entries()
956 intel_private.driver->write_entry(intel_private.scratch_page_dma, in intel_gtt_clear_range()
972 if (intel_private.needs_dmar) { in intel_fake_agp_remove_entries()
987 if (pg_count != intel_private.num_dcache_entries) in intel_fake_agp_alloc_by_type()
1010 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, in intel_alloc_chipset_flush_resource()
1012 pcibios_align_resource, intel_private.bridge_dev); in intel_alloc_chipset_flush_resource()
1022 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); in intel_i915_setup_chipset_flush()
1025 intel_private.resource_valid = 1; in intel_i915_setup_chipset_flush()
1026 …pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start &… in intel_i915_setup_chipset_flush()
1030 intel_private.resource_valid = 1; in intel_i915_setup_chipset_flush()
1031 intel_private.ifp_resource.start = temp; in intel_i915_setup_chipset_flush()
1032 intel_private.ifp_resource.end = temp + PAGE_SIZE; in intel_i915_setup_chipset_flush()
1033 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); in intel_i915_setup_chipset_flush()
1036 intel_private.resource_valid = 0; in intel_i915_setup_chipset_flush()
1045 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); in intel_i965_g33_setup_chipset_flush()
1046 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); in intel_i965_g33_setup_chipset_flush()
1052 intel_private.resource_valid = 1; in intel_i965_g33_setup_chipset_flush()
1053 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, in intel_i965_g33_setup_chipset_flush()
1054 upper_32_bits(intel_private.ifp_resource.start)); in intel_i965_g33_setup_chipset_flush()
1055 …pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start &… in intel_i965_g33_setup_chipset_flush()
1062 intel_private.resource_valid = 1; in intel_i965_g33_setup_chipset_flush()
1063 intel_private.ifp_resource.start = l64; in intel_i965_g33_setup_chipset_flush()
1064 intel_private.ifp_resource.end = l64 + PAGE_SIZE; in intel_i965_g33_setup_chipset_flush()
1065 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); in intel_i965_g33_setup_chipset_flush()
1068 intel_private.resource_valid = 0; in intel_i965_g33_setup_chipset_flush()
1075 if (intel_private.ifp_resource.start) in intel_i9xx_setup_flush()
1082 intel_private.ifp_resource.name = "Intel Flush Page"; in intel_i9xx_setup_flush()
1083 intel_private.ifp_resource.flags = IORESOURCE_MEM; in intel_i9xx_setup_flush()
1092 if (intel_private.ifp_resource.start) in intel_i9xx_setup_flush()
1093 intel_private.i9xx_flush_page = ioremap(intel_private.ifp_resource.start, PAGE_SIZE); in intel_i9xx_setup_flush()
1094 if (!intel_private.i9xx_flush_page) in intel_i9xx_setup_flush()
1095 dev_err(&intel_private.pcidev->dev, in intel_i9xx_setup_flush()
1101 if (intel_private.i9xx_flush_page) in i9xx_cleanup()
1102 iounmap(intel_private.i9xx_flush_page); in i9xx_cleanup()
1103 if (intel_private.resource_valid) in i9xx_cleanup()
1104 release_resource(&intel_private.ifp_resource); in i9xx_cleanup()
1105 intel_private.ifp_resource.start = 0; in i9xx_cleanup()
1106 intel_private.resource_valid = 0; in i9xx_cleanup()
1112 if (intel_private.i9xx_flush_page) in i9xx_chipset_flush()
1113 writel(1, intel_private.i9xx_flush_page); in i9xx_chipset_flush()
1128 writel_relaxed(addr | pte_flags, intel_private.gtt + entry); in i965_write_entry()
1136 reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR); in i9xx_setup()
1138 intel_private.registers = ioremap(reg_addr, size); in i9xx_setup()
1139 if (!intel_private.registers) in i9xx_setup()
1144 intel_private.gtt_phys_addr = in i9xx_setup()
1145 pci_resource_start(intel_private.pcidev, I915_PTE_BAR); in i9xx_setup()
1148 intel_private.gtt_phys_addr = reg_addr + MB(2); in i9xx_setup()
1151 intel_private.gtt_phys_addr = reg_addr + KB(512); in i9xx_setup()
1359 intel_private.pcidev = gmch_device; in find_gmch()
1372 intel_private.pcidev = pci_dev_get(gpu_pdev); in intel_gmch_probe()
1373 intel_private.driver = in intel_gmch_probe()
1379 intel_private.driver = in intel_gmch_probe()
1385 if (!intel_private.driver) in intel_gmch_probe()
1394 bridge->dev_private_data = &intel_private; in intel_gmch_probe()
1405 if (intel_private.refcount++) in intel_gmch_probe()
1408 intel_private.bridge_dev = pci_dev_get(bridge_pdev); in intel_gmch_probe()
1413 mask = intel_private.driver->dma_mask_size; in intel_gmch_probe()
1414 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) in intel_gmch_probe()
1415 dev_err(&intel_private.pcidev->dev, in intel_gmch_probe()
1419 pci_set_consistent_dma_mask(intel_private.pcidev, in intel_gmch_probe()
1437 *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; in intel_gtt_get()
1438 *mappable_base = intel_private.gma_bus_addr; in intel_gtt_get()
1439 *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT; in intel_gtt_get()
1445 if (intel_private.driver->chipset_flush) in intel_gtt_chipset_flush()
1446 intel_private.driver->chipset_flush(); in intel_gtt_chipset_flush()
1452 if (--intel_private.refcount) in intel_gmch_remove()
1455 if (intel_private.scratch_page) in intel_gmch_remove()
1457 if (intel_private.pcidev) in intel_gmch_remove()
1458 pci_dev_put(intel_private.pcidev); in intel_gmch_remove()
1459 if (intel_private.bridge_dev) in intel_gmch_remove()
1460 pci_dev_put(intel_private.bridge_dev); in intel_gmch_remove()
1461 intel_private.driver = NULL; in intel_gmch_remove()