Lines Matching refs:base_address
97 out_be32(drvdata->base_address + XHI_WF_OFFSET, data); in fifo_icap_fifo_write()
108 u32 data = in_be32(drvdata->base_address + XHI_RF_OFFSET); in fifo_icap_fifo_read()
121 out_be32(drvdata->base_address + XHI_SZ_OFFSET, data); in fifo_icap_set_read_size()
130 out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_WRITE_MASK); in fifo_icap_start_config()
140 out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_READ_MASK); in fifo_icap_start_readback()
162 u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET); in fifo_icap_get_status()
173 u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET); in fifo_icap_busy()
186 return in_be32(drvdata->base_address + XHI_WFV_OFFSET); in fifo_icap_write_fifo_vacancy()
198 return in_be32(drvdata->base_address + XHI_RFO_OFFSET); in fifo_icap_read_fifo_occupancy()
364 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_reset()
366 out_be32(drvdata->base_address + XHI_CR_OFFSET, in fifo_icap_reset()
369 out_be32(drvdata->base_address + XHI_CR_OFFSET, in fifo_icap_reset()
385 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_flush_fifo()
387 out_be32(drvdata->base_address + XHI_CR_OFFSET, in fifo_icap_flush_fifo()
390 out_be32(drvdata->base_address + XHI_CR_OFFSET, in fifo_icap_flush_fifo()