Lines Matching refs:OWL_DIVIDER_HW
222 OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
228 OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
258 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
282 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
288 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
294 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
300 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
306 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
312 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
318 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
324 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
330 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
336 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
342 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
348 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
354 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
372 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
378 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
384 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
395 OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
404 OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),