Lines Matching refs:ctl_reg
490 u32 ctl_reg; member
511 u32 ctl_reg; member
930 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; in bcm2835_clock_is_on()
1024 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { in bcm2835_clock_wait_busy()
1041 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_off()
1042 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); in bcm2835_clock_off()
1056 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_on()
1057 cprman_read(cprman, data->ctl_reg) | in bcm2835_clock_on()
1095 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; in bcm2835_clock_set_rate()
1097 cprman_write(cprman, data->ctl_reg, ctl); in bcm2835_clock_set_rate()
1245 cprman_write(cprman, data->ctl_reg, src); in bcm2835_clock_set_parent()
1254 u32 src = cprman_read(cprman, data->ctl_reg); in bcm2835_clock_get_parent()
1277 bcm2835_debugfs_regset(cprman, data->ctl_reg, in bcm2835_clock_debug_init()
1455 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE)) in bcm2835_register_clock()
1481 cprman->regs + gate_data->ctl_reg, in bcm2835_register_gate()
1920 .ctl_reg = CM_OTPCTL,
1932 .ctl_reg = CM_TIMERCTL,
1943 .ctl_reg = CM_TSENSCTL,
1950 .ctl_reg = CM_TECCTL,
1959 .ctl_reg = CM_H264CTL,
1967 .ctl_reg = CM_ISPCTL,
1980 .ctl_reg = CM_SDCCTL,
1988 .ctl_reg = CM_V3DCTL,
2002 .ctl_reg = CM_VPUCTL,
2014 .ctl_reg = CM_AVEOCTL,
2022 .ctl_reg = CM_CAM0CTL,
2030 .ctl_reg = CM_CAM1CTL,
2038 .ctl_reg = CM_DFTCTL,
2045 .ctl_reg = CM_DPICTL,
2055 .ctl_reg = CM_EMMCCTL,
2065 .ctl_reg = CM_EMMC2CTL,
2075 .ctl_reg = CM_GP0CTL,
2084 .ctl_reg = CM_GP1CTL,
2094 .ctl_reg = CM_GP2CTL,
2104 .ctl_reg = CM_HSMCTL,
2112 .ctl_reg = CM_PCMCTL,
2122 .ctl_reg = CM_PWMCTL,
2131 .ctl_reg = CM_SLIMCTL,
2140 .ctl_reg = CM_SMICTL,
2148 .ctl_reg = CM_UARTCTL,
2158 .ctl_reg = CM_VECCTL,
2173 .ctl_reg = CM_DSI0ECTL,
2181 .ctl_reg = CM_DSI1ECTL,
2189 .ctl_reg = CM_DSI0PCTL,
2197 .ctl_reg = CM_DSI1PCTL,
2215 .ctl_reg = CM_PERIICTL),