Lines Matching refs:ARRAY_SIZE
419 ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT,
422 ARRAY_SIZE(clk_mux_vcodecbus_p), CLK_SET_RATE_PARENT,
425 ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT,
428 ARRAY_SIZE(clk_mux_sd_pll_p), CLK_SET_RATE_PARENT,
431 ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT,
434 ARRAY_SIZE(clk_mux_sdio_pll_p), CLK_SET_RATE_PARENT,
437 ARRAY_SIZE(clk_mux_a53hpm_p), CLK_SET_RATE_PARENT,
440 ARRAY_SIZE(clk_mux_320m_p), CLK_SET_RATE_PARENT,
443 ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT,
446 ARRAY_SIZE(clk_mux_uartl_p), CLK_SET_RATE_PARENT,
449 ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT,
452 ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT,
455 ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT,
458 ARRAY_SIZE(clk_mux_pcieaxi_p), CLK_SET_RATE_PARENT,
461 ARRAY_SIZE(clk_mux_ao_asp_p), CLK_SET_RATE_PARENT,
464 ARRAY_SIZE(clk_mux_vdec_p), CLK_SET_RATE_PARENT,
467 ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT,
470 ARRAY_SIZE(clk_isp_snclk_mux0_p), CLK_SET_RATE_PARENT,
473 ARRAY_SIZE(clk_isp_snclk_mux1_p), CLK_SET_RATE_PARENT,
476 ARRAY_SIZE(clk_isp_snclk_mux2_p), CLK_SET_RATE_PARENT,
479 ARRAY_SIZE(clk_mux_rxdphy_cfg_p), CLK_SET_RATE_PARENT,
482 ARRAY_SIZE(clk_mux_ics_p), CLK_SET_RATE_PARENT,
635 ARRAY_SIZE(clk_mux_ufs_subsys_p), CLK_SET_RATE_PARENT,
638 ARRAY_SIZE(clk_mux_clkout0_p), CLK_SET_RATE_PARENT,
641 ARRAY_SIZE(clk_mux_clkout1_p), CLK_SET_RATE_PARENT,
644 clk_mux_asp_subsys_peri_p, ARRAY_SIZE(clk_mux_asp_subsys_peri_p),
647 ARRAY_SIZE(clk_mux_asp_pll_p), CLK_SET_RATE_PARENT,
784 ARRAY_SIZE(clk_mux_vivobus_p), CLK_SET_RATE_PARENT,
787 ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT,
790 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT,
793 ARRAY_SIZE(clk_mux_ldi1_p), CLK_SET_RATE_PARENT,
796 ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT,
829 int nr = ARRAY_SIZE(hi3670_fixed_rate_clks) + in hi3670_clk_crgctrl_init()
830 ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks) + in hi3670_clk_crgctrl_init()
831 ARRAY_SIZE(hi3670_crgctrl_gate_clks) + in hi3670_clk_crgctrl_init()
832 ARRAY_SIZE(hi3670_crgctrl_mux_clks) + in hi3670_clk_crgctrl_init()
833 ARRAY_SIZE(hi3670_crg_fixed_factor_clks) + in hi3670_clk_crgctrl_init()
834 ARRAY_SIZE(hi3670_crgctrl_divider_clks); in hi3670_clk_crgctrl_init()
841 ARRAY_SIZE(hi3670_fixed_rate_clks), in hi3670_clk_crgctrl_init()
844 ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks), in hi3670_clk_crgctrl_init()
847 ARRAY_SIZE(hi3670_crgctrl_gate_clks), in hi3670_clk_crgctrl_init()
850 ARRAY_SIZE(hi3670_crgctrl_mux_clks), in hi3670_clk_crgctrl_init()
853 ARRAY_SIZE(hi3670_crg_fixed_factor_clks), in hi3670_clk_crgctrl_init()
856 ARRAY_SIZE(hi3670_crgctrl_divider_clks), in hi3670_clk_crgctrl_init()
863 int nr = ARRAY_SIZE(hi3670_pctrl_gate_clks); in hi3670_clk_pctrl_init()
869 ARRAY_SIZE(hi3670_pctrl_gate_clks), clk_data); in hi3670_clk_pctrl_init()
875 int nr = ARRAY_SIZE(hi3670_pmu_gate_clks); in hi3670_clk_pmuctrl_init()
882 ARRAY_SIZE(hi3670_pmu_gate_clks), clk_data); in hi3670_clk_pmuctrl_init()
888 int nr = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks) + in hi3670_clk_sctrl_init()
889 ARRAY_SIZE(hi3670_sctrl_gate_clks) + in hi3670_clk_sctrl_init()
890 ARRAY_SIZE(hi3670_sctrl_mux_clks) + in hi3670_clk_sctrl_init()
891 ARRAY_SIZE(hi3670_sctrl_divider_clks); in hi3670_clk_sctrl_init()
898 ARRAY_SIZE(hi3670_sctrl_gate_sep_clks), in hi3670_clk_sctrl_init()
901 ARRAY_SIZE(hi3670_sctrl_gate_clks), in hi3670_clk_sctrl_init()
904 ARRAY_SIZE(hi3670_sctrl_mux_clks), in hi3670_clk_sctrl_init()
907 ARRAY_SIZE(hi3670_sctrl_divider_clks), in hi3670_clk_sctrl_init()
914 int nr = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks) + in hi3670_clk_iomcu_init()
915 ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks); in hi3670_clk_iomcu_init()
922 ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), clk_data); in hi3670_clk_iomcu_init()
925 ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks), in hi3670_clk_iomcu_init()
933 int nr = ARRAY_SIZE(hi3670_media1_gate_sep_clks) + in hi3670_clk_media1_init()
934 ARRAY_SIZE(hi3670_media1_gate_clks) + in hi3670_clk_media1_init()
935 ARRAY_SIZE(hi3670_media1_mux_clks) + in hi3670_clk_media1_init()
936 ARRAY_SIZE(hi3670_media1_divider_clks); in hi3670_clk_media1_init()
943 ARRAY_SIZE(hi3670_media1_gate_sep_clks), in hi3670_clk_media1_init()
946 ARRAY_SIZE(hi3670_media1_gate_clks), in hi3670_clk_media1_init()
949 ARRAY_SIZE(hi3670_media1_mux_clks), in hi3670_clk_media1_init()
952 ARRAY_SIZE(hi3670_media1_divider_clks), in hi3670_clk_media1_init()
960 int nr = ARRAY_SIZE(hi3670_media2_gate_sep_clks); in hi3670_clk_media2_init()
967 ARRAY_SIZE(hi3670_media2_gate_sep_clks), in hi3670_clk_media2_init()