Lines Matching defs:name
75 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ argument
78 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
83 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ argument
86 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
89 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
92 #define imx_clk_fixed(name, rate) \ argument
95 #define imx_clk_fixed_factor(name, parent, mult, div) \ argument
98 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
101 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ argument
104 #define imx_clk_gate(name, parent, reg, shift) \ argument
107 #define imx_clk_gate_dis(name, parent, reg, shift) \ argument
110 #define imx_clk_gate2(name, parent, reg, shift) \ argument
113 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \ argument
116 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ argument
119 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ argument
122 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
125 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
128 #define imx_clk_pllv1(type, name, parent, base) \ argument
131 #define imx_clk_pllv2(name, parent, base) \ argument
134 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
137 #define imx_clk_hw_gate(name, parent, reg, shift) \ argument
140 #define imx_clk_hw_gate2(name, parent, reg, shift) \ argument
143 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \ argument
146 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \ argument
149 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \ argument
152 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \ argument
155 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \ argument
158 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \ argument
161 #define imx_clk_hw_gate3(name, parent, reg, shift) \ argument
164 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \ argument
167 #define imx_clk_hw_gate4(name, parent, reg, shift) \ argument
170 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \ argument
173 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \ argument
176 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \ argument
179 #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
182 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \ argument
185 #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
188 #define imx_clk_hw_divider(name, parent, reg, shift, width) \ argument
191 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \ argument
195 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \ argument
198 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \ argument
316 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) in imx_clk_hw_fixed()
321 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name, in imx_clk_hw_fixed_factor()
328 static inline struct clk_hw *__imx_clk_hw_divider(const char *name, in __imx_clk_hw_divider()
337 static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent, in __imx_clk_hw_gate()
346 static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent, in __imx_clk_hw_gate2()
355 static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg, in __imx_clk_hw_mux()
388 #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \ argument
392 #define imx8m_clk_hw_composite(name, parent_names, reg) \ argument
396 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \ argument
400 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \ argument
404 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \ argument
408 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \ argument
412 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \ argument
417 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \ argument