Lines Matching refs:CGU_CLK_MUX
329 "sclk_a", CGU_CLK_MUX,
336 "cpumux", CGU_CLK_MUX,
355 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
363 "ahb2_apb_mux", CGU_CLK_MUX,
382 "ddr", CGU_CLK_MUX | CGU_CLK_DIV,
389 "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
398 "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
405 "i2s", CGU_CLK_MUX,
411 "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
419 "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
427 "msc_mux", CGU_CLK_MUX,
454 "uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
463 "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
470 "ssi", CGU_CLK_MUX,
476 "cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV,
483 "pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV,
491 "pcm", CGU_CLK_MUX | CGU_CLK_GATE,
498 "gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
507 "hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
516 "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
531 "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,