Lines Matching refs:GATE_BDP0
27 #define GATE_BDP0(_id, _name, _parent, _shift) { \ macro
46 GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
47 GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
48 GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
49 GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),
50 GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),
51 GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),
52 GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),
53 GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7),
54 GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),
55 GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),
56 GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),
57 GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),
58 GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),
59 GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),
60 GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),
61 GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),
62 GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),
63 GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),
64 GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),
65 GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),
66 GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),
67 GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),
68 GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),
69 GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),
70 GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),
71 GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),
72 GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
73 GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),
74 GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),
75 GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),
76 GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),
77 GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),