Lines Matching refs:mux
23 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); in mtk_clk_mux_enable_setclr() local
26 if (mux->lock) in mtk_clk_mux_enable_setclr()
27 spin_lock_irqsave(mux->lock, flags); in mtk_clk_mux_enable_setclr()
29 __acquire(mux->lock); in mtk_clk_mux_enable_setclr()
31 regmap_write(mux->regmap, mux->data->clr_ofs, in mtk_clk_mux_enable_setclr()
32 BIT(mux->data->gate_shift)); in mtk_clk_mux_enable_setclr()
39 if (mux->reparent && mux->data->upd_shift >= 0) { in mtk_clk_mux_enable_setclr()
40 regmap_write(mux->regmap, mux->data->upd_ofs, in mtk_clk_mux_enable_setclr()
41 BIT(mux->data->upd_shift)); in mtk_clk_mux_enable_setclr()
42 mux->reparent = false; in mtk_clk_mux_enable_setclr()
45 if (mux->lock) in mtk_clk_mux_enable_setclr()
46 spin_unlock_irqrestore(mux->lock, flags); in mtk_clk_mux_enable_setclr()
48 __release(mux->lock); in mtk_clk_mux_enable_setclr()
55 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); in mtk_clk_mux_disable_setclr() local
57 regmap_write(mux->regmap, mux->data->set_ofs, in mtk_clk_mux_disable_setclr()
58 BIT(mux->data->gate_shift)); in mtk_clk_mux_disable_setclr()
63 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); in mtk_clk_mux_is_enabled() local
66 regmap_read(mux->regmap, mux->data->mux_ofs, &val); in mtk_clk_mux_is_enabled()
68 return (val & BIT(mux->data->gate_shift)) == 0; in mtk_clk_mux_is_enabled()
73 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); in mtk_clk_mux_get_parent() local
74 u32 mask = GENMASK(mux->data->mux_width - 1, 0); in mtk_clk_mux_get_parent()
77 regmap_read(mux->regmap, mux->data->mux_ofs, &val); in mtk_clk_mux_get_parent()
78 val = (val >> mux->data->mux_shift) & mask; in mtk_clk_mux_get_parent()
85 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); in mtk_clk_mux_set_parent_setclr_lock() local
86 u32 mask = GENMASK(mux->data->mux_width - 1, 0); in mtk_clk_mux_set_parent_setclr_lock()
90 if (mux->lock) in mtk_clk_mux_set_parent_setclr_lock()
91 spin_lock_irqsave(mux->lock, flags); in mtk_clk_mux_set_parent_setclr_lock()
93 __acquire(mux->lock); in mtk_clk_mux_set_parent_setclr_lock()
95 regmap_read(mux->regmap, mux->data->mux_ofs, &orig); in mtk_clk_mux_set_parent_setclr_lock()
96 val = (orig & ~(mask << mux->data->mux_shift)) in mtk_clk_mux_set_parent_setclr_lock()
97 | (index << mux->data->mux_shift); in mtk_clk_mux_set_parent_setclr_lock()
100 regmap_write(mux->regmap, mux->data->clr_ofs, in mtk_clk_mux_set_parent_setclr_lock()
101 mask << mux->data->mux_shift); in mtk_clk_mux_set_parent_setclr_lock()
102 regmap_write(mux->regmap, mux->data->set_ofs, in mtk_clk_mux_set_parent_setclr_lock()
103 index << mux->data->mux_shift); in mtk_clk_mux_set_parent_setclr_lock()
105 if (mux->data->upd_shift >= 0) { in mtk_clk_mux_set_parent_setclr_lock()
106 regmap_write(mux->regmap, mux->data->upd_ofs, in mtk_clk_mux_set_parent_setclr_lock()
107 BIT(mux->data->upd_shift)); in mtk_clk_mux_set_parent_setclr_lock()
108 mux->reparent = true; in mtk_clk_mux_set_parent_setclr_lock()
112 if (mux->lock) in mtk_clk_mux_set_parent_setclr_lock()
113 spin_unlock_irqrestore(mux->lock, flags); in mtk_clk_mux_set_parent_setclr_lock()
115 __release(mux->lock); in mtk_clk_mux_set_parent_setclr_lock()
135 static struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, in mtk_clk_register_mux() argument
147 init.name = mux->name; in mtk_clk_register_mux()
148 init.flags = mux->flags | CLK_SET_RATE_PARENT; in mtk_clk_register_mux()
149 init.parent_names = mux->parent_names; in mtk_clk_register_mux()
150 init.num_parents = mux->num_parents; in mtk_clk_register_mux()
151 init.ops = mux->ops; in mtk_clk_register_mux()
154 clk_mux->data = mux; in mtk_clk_register_mux()
184 const struct mtk_mux *mux = &muxes[i]; in mtk_clk_register_muxes() local
186 if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) { in mtk_clk_register_muxes()
187 clk = mtk_clk_register_mux(mux, regmap, lock); in mtk_clk_register_muxes()
191 mux->name, PTR_ERR(clk)); in mtk_clk_register_muxes()
195 clk_data->clks[mux->id] = clk; in mtk_clk_register_muxes()