Lines Matching refs:CLK_SET_RATE_PARENT
119 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
123 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
127 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
131 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
135 CLK_SET_RATE_PARENT, 1, 5); in mmp2_clk_init()
139 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
143 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
147 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
151 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
155 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
159 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
163 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
167 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
171 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
175 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
179 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
183 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
247 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
258 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
269 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
280 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
291 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
301 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
311 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
321 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
331 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
336 CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, in mmp2_clk_init()
362 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
367 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, in mmp2_clk_init()
385 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
390 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1, in mmp2_clk_init()
404 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
409 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
422 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
432 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
437 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, in mmp2_clk_init()
450 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, in mmp2_clk_init()