Lines Matching refs:pll_regs
141 const struct cpu_dfs_regs *pll_regs; member
151 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_recalc_rate()
152 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_recalc_rate()
154 cpu_clkdiv_ratio &= clk->pll_regs->divider_mask; in ap_cpu_clk_recalc_rate()
155 cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset; in ap_cpu_clk_recalc_rate()
167 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_set_rate()
168 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_set_rate()
169 cpu_force_reg = clk->pll_regs->force_reg + in ap_cpu_clk_set_rate()
170 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_set_rate()
171 cpu_ratio_reg = clk->pll_regs->ratio_reg + in ap_cpu_clk_set_rate()
172 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_set_rate()
175 reg &= ~(clk->pll_regs->divider_mask); in ap_cpu_clk_set_rate()
176 reg |= (divider << clk->pll_regs->divider_offset); in ap_cpu_clk_set_rate()
182 if (clk->pll_regs->divider_ratio) { in ap_cpu_clk_set_rate()
184 reg |= ((divider * clk->pll_regs->divider_ratio) << in ap_cpu_clk_set_rate()
191 clk->pll_regs->force_mask, in ap_cpu_clk_set_rate()
192 clk->pll_regs->force_mask); in ap_cpu_clk_set_rate()
195 BIT(clk->pll_regs->ratio_offset), in ap_cpu_clk_set_rate()
196 BIT(clk->pll_regs->ratio_offset)); in ap_cpu_clk_set_rate()
198 stable_bit = BIT(clk->pll_regs->ratio_state_offset + in ap_cpu_clk_set_rate()
200 clk->pll_regs->ratio_state_cluster_offset); in ap_cpu_clk_set_rate()
202 clk->pll_regs->ratio_state_reg, reg, in ap_cpu_clk_set_rate()
209 BIT(clk->pll_regs->ratio_offset), 0); in ap_cpu_clk_set_rate()
320 ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev); in ap_cpu_clock_probe()