Lines Matching refs:cpuclk
208 struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); in clk_cpu_8996_mux_get_parent() local
209 u32 mask = GENMASK(cpuclk->width - 1, 0); in clk_cpu_8996_mux_get_parent()
212 regmap_read(clkr->regmap, cpuclk->reg, &val); in clk_cpu_8996_mux_get_parent()
213 val >>= cpuclk->shift; in clk_cpu_8996_mux_get_parent()
221 struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); in clk_cpu_8996_mux_set_parent() local
222 u32 mask = GENMASK(cpuclk->width + cpuclk->shift - 1, cpuclk->shift); in clk_cpu_8996_mux_set_parent()
226 val <<= cpuclk->shift; in clk_cpu_8996_mux_set_parent()
228 return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val); in clk_cpu_8996_mux_set_parent()
234 struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); in clk_cpu_8996_mux_determine_rate() local
235 struct clk_hw *parent = cpuclk->pll; in clk_cpu_8996_mux_determine_rate()
237 if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { in clk_cpu_8996_mux_determine_rate()
241 parent = cpuclk->pll_div_2; in clk_cpu_8996_mux_determine_rate()
459 struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb); in cpu_clk_notifier_cb() local
465 ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); in cpu_clk_notifier_cb()
470 ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, in cpu_clk_notifier_cb()
473 ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, in cpu_clk_notifier_cb()