Lines Matching refs:DEF_FIXED
120 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
121 DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1),
122 DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1),
123 DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1),
124 DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1),
125 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
126 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
127 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
128 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
129 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
139 DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
140 DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
141 DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
142 DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1),
143 DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1),
144 DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1),
145 DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1),
146 DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1),
147 DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1),
148 DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1),
149 DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1),
150 DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
151 DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1),
152 DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1),
153 DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1),
154 DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1),
155 DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1),
156 DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1),
157 DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
158 DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
159 DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
160 DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1),