Lines Matching refs:r
63 static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r) in __prci_wrpll_unpack() argument
67 v = r & PRCI_COREPLLCFG0_DIVR_MASK; in __prci_wrpll_unpack()
71 v = r & PRCI_COREPLLCFG0_DIVF_MASK; in __prci_wrpll_unpack()
75 v = r & PRCI_COREPLLCFG0_DIVQ_MASK; in __prci_wrpll_unpack()
79 v = r & PRCI_COREPLLCFG0_RANGE_MASK; in __prci_wrpll_unpack()
107 u32 r = 0; in __prci_wrpll_pack() local
109 r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; in __prci_wrpll_pack()
110 r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; in __prci_wrpll_pack()
111 r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; in __prci_wrpll_pack()
112 r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; in __prci_wrpll_pack()
115 r |= PRCI_COREPLLCFG0_FSE_MASK; in __prci_wrpll_pack()
117 return r; in __prci_wrpll_pack()
212 int r; in sifive_prci_wrpll_set_rate() local
214 r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); in sifive_prci_wrpll_set_rate()
215 if (r) in sifive_prci_wrpll_set_rate()
216 return r; in sifive_prci_wrpll_set_rate()
233 u32 r; in sifive_clk_is_enabled() local
235 r = __prci_readl(pd, pwd->cfg1_offs); in sifive_clk_is_enabled()
237 if (r & PRCI_COREPLLCFG1_CKE_MASK) in sifive_clk_is_enabled()
265 u32 r; in sifive_prci_clock_disable() local
270 r = __prci_readl(pd, pwd->cfg1_offs); in sifive_prci_clock_disable()
271 r &= ~PRCI_COREPLLCFG1_CKE_MASK; in sifive_prci_clock_disable()
273 __prci_wrpll_write_cfg1(pd, pwd, r); in sifive_prci_clock_disable()
320 u32 r; in sifive_prci_coreclksel_use_hfclk() local
322 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); in sifive_prci_coreclksel_use_hfclk()
323 r |= PRCI_CORECLKSEL_CORECLKSEL_MASK; in sifive_prci_coreclksel_use_hfclk()
324 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); in sifive_prci_coreclksel_use_hfclk()
326 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ in sifive_prci_coreclksel_use_hfclk()
341 u32 r; in sifive_prci_coreclksel_use_corepll() local
343 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); in sifive_prci_coreclksel_use_corepll()
344 r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; in sifive_prci_coreclksel_use_corepll()
345 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); in sifive_prci_coreclksel_use_corepll()
347 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ in sifive_prci_coreclksel_use_corepll()
363 u32 r; in sifive_prci_coreclksel_use_final_corepll() local
365 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); in sifive_prci_coreclksel_use_final_corepll()
366 r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; in sifive_prci_coreclksel_use_final_corepll()
367 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); in sifive_prci_coreclksel_use_final_corepll()
369 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ in sifive_prci_coreclksel_use_final_corepll()
384 u32 r; in sifive_prci_corepllsel_use_dvfscorepll() local
386 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); in sifive_prci_corepllsel_use_dvfscorepll()
387 r |= PRCI_COREPLLSEL_COREPLLSEL_MASK; in sifive_prci_corepllsel_use_dvfscorepll()
388 __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd); in sifive_prci_corepllsel_use_dvfscorepll()
390 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */ in sifive_prci_corepllsel_use_dvfscorepll()
405 u32 r; in sifive_prci_corepllsel_use_corepll() local
407 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); in sifive_prci_corepllsel_use_corepll()
408 r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK; in sifive_prci_corepllsel_use_corepll()
409 __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd); in sifive_prci_corepllsel_use_corepll()
411 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */ in sifive_prci_corepllsel_use_corepll()
426 u32 r; in sifive_prci_hfpclkpllsel_use_hfclk() local
428 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); in sifive_prci_hfpclkpllsel_use_hfclk()
429 r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK; in sifive_prci_hfpclkpllsel_use_hfclk()
430 __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd); in sifive_prci_hfpclkpllsel_use_hfclk()
432 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ in sifive_prci_hfpclkpllsel_use_hfclk()
447 u32 r; in sifive_prci_hfpclkpllsel_use_hfpclkpll() local
449 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); in sifive_prci_hfpclkpllsel_use_hfpclkpll()
450 r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK; in sifive_prci_hfpclkpllsel_use_hfpclkpll()
451 __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd); in sifive_prci_hfpclkpllsel_use_hfpclkpll()
453 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ in sifive_prci_hfpclkpllsel_use_hfpclkpll()
461 u32 r; in sifive_prci_pcie_aux_clock_is_enabled() local
463 r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); in sifive_prci_pcie_aux_clock_is_enabled()
465 if (r & PRCI_PCIE_AUX_EN_MASK) in sifive_prci_pcie_aux_clock_is_enabled()
475 u32 r __maybe_unused; in sifive_prci_pcie_aux_clock_enable()
481 r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */ in sifive_prci_pcie_aux_clock_enable()
490 u32 r __maybe_unused; in sifive_prci_pcie_aux_clock_disable()
493 r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */ in sifive_prci_pcie_aux_clock_disable()
513 int parent_count, i, r; in __prci_register_clocks() local
537 r = devm_clk_hw_register(dev, &pic->hw); in __prci_register_clocks()
538 if (r) { in __prci_register_clocks()
540 init.name, r); in __prci_register_clocks()
541 return r; in __prci_register_clocks()
544 r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev)); in __prci_register_clocks()
545 if (r) { in __prci_register_clocks()
547 init.name, r); in __prci_register_clocks()
548 return r; in __prci_register_clocks()
556 r = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, in __prci_register_clocks()
558 if (r) { in __prci_register_clocks()
559 dev_err(dev, "could not add hw_provider: %d\n", r); in __prci_register_clocks()
560 return r; in __prci_register_clocks()
578 int r; in sifive_prci_probe() local
599 r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev); in sifive_prci_probe()
600 if (r) { in sifive_prci_probe()
601 dev_err(dev, "could not register reset controller: %d\n", r); in sifive_prci_probe()
602 return r; in sifive_prci_probe()
604 r = __prci_register_clocks(dev, pd, desc); in sifive_prci_probe()
605 if (r) { in sifive_prci_probe()
606 dev_err(dev, "could not register clocks: %d\n", r); in sifive_prci_probe()
607 return r; in sifive_prci_probe()