Lines Matching refs:td
330 static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs) in dfll_readl() argument
332 return __raw_readl(td->base + offs); in dfll_readl()
335 static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs) in dfll_writel() argument
338 __raw_writel(val, td->base + offs); in dfll_writel()
341 static inline void dfll_wmb(struct tegra_dfll *td) in dfll_wmb() argument
343 dfll_readl(td, DFLL_CTRL); in dfll_wmb()
348 static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs) in dfll_i2c_readl() argument
350 return __raw_readl(td->i2c_base + offs); in dfll_i2c_readl()
353 static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs) in dfll_i2c_writel() argument
355 __raw_writel(val, td->i2c_base + offs); in dfll_i2c_writel()
358 static inline void dfll_i2c_wmb(struct tegra_dfll *td) in dfll_i2c_wmb() argument
360 dfll_i2c_readl(td, DFLL_I2C_CFG); in dfll_i2c_wmb()
370 static bool dfll_is_running(struct tegra_dfll *td) in dfll_is_running() argument
372 return td->mode >= DFLL_OPEN_LOOP; in dfll_is_running()
390 struct tegra_dfll *td = dev_get_drvdata(dev); in tegra_dfll_runtime_resume() local
393 ret = clk_enable(td->ref_clk); in tegra_dfll_runtime_resume()
399 ret = clk_enable(td->soc_clk); in tegra_dfll_runtime_resume()
402 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
406 ret = clk_enable(td->i2c_clk); in tegra_dfll_runtime_resume()
409 clk_disable(td->soc_clk); in tegra_dfll_runtime_resume()
410 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
427 struct tegra_dfll *td = dev_get_drvdata(dev); in tegra_dfll_runtime_suspend() local
429 clk_disable(td->ref_clk); in tegra_dfll_runtime_suspend()
430 clk_disable(td->soc_clk); in tegra_dfll_runtime_suspend()
431 clk_disable(td->i2c_clk); in tegra_dfll_runtime_suspend()
449 static void dfll_tune_low(struct tegra_dfll *td) in dfll_tune_low() argument
451 td->tune_range = DFLL_TUNE_LOW; in dfll_tune_low()
453 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0); in dfll_tune_low()
454 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1); in dfll_tune_low()
455 dfll_wmb(td); in dfll_tune_low()
457 if (td->soc->set_clock_trimmers_low) in dfll_tune_low()
458 td->soc->set_clock_trimmers_low(); in dfll_tune_low()
491 static void dfll_set_mode(struct tegra_dfll *td, in dfll_set_mode() argument
494 td->mode = mode; in dfll_set_mode()
495 dfll_writel(td, mode - 1, DFLL_CTRL); in dfll_set_mode()
496 dfll_wmb(td); in dfll_set_mode()
503 static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min) in get_dvco_rate_below() argument
509 min_uv = td->lut_uv[out_min]; in get_dvco_rate_below()
511 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in get_dvco_rate_below()
539 static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable) in dfll_i2c_set_output_enabled() argument
543 val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG); in dfll_i2c_set_output_enabled()
550 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG); in dfll_i2c_set_output_enabled()
551 dfll_i2c_wmb(td); in dfll_i2c_set_output_enabled()
570 static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable) in dfll_pwm_set_output_enabled() argument
576 ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state); in dfll_pwm_set_output_enabled()
578 dev_err(td->dev, "setting enable state failed\n"); in dfll_pwm_set_output_enabled()
581 val = dfll_readl(td, DFLL_OUTPUT_CFG); in dfll_pwm_set_output_enabled()
583 div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate); in dfll_pwm_set_output_enabled()
586 dfll_writel(td, val, DFLL_OUTPUT_CFG); in dfll_pwm_set_output_enabled()
587 dfll_wmb(td); in dfll_pwm_set_output_enabled()
590 dfll_writel(td, val, DFLL_OUTPUT_CFG); in dfll_pwm_set_output_enabled()
591 dfll_wmb(td); in dfll_pwm_set_output_enabled()
593 ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state); in dfll_pwm_set_output_enabled()
595 dev_warn(td->dev, "setting disable state failed\n"); in dfll_pwm_set_output_enabled()
597 val = dfll_readl(td, DFLL_OUTPUT_CFG); in dfll_pwm_set_output_enabled()
599 dfll_writel(td, val, DFLL_OUTPUT_CFG); in dfll_pwm_set_output_enabled()
600 dfll_wmb(td); in dfll_pwm_set_output_enabled()
614 static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val) in dfll_set_force_output_value() argument
616 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE); in dfll_set_force_output_value()
619 dfll_writel(td, val, DFLL_OUTPUT_FORCE); in dfll_set_force_output_value()
620 dfll_wmb(td); in dfll_set_force_output_value()
622 return dfll_readl(td, DFLL_OUTPUT_FORCE); in dfll_set_force_output_value()
632 static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable) in dfll_set_force_output_enabled() argument
634 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE); in dfll_set_force_output_enabled()
641 dfll_writel(td, val, DFLL_OUTPUT_FORCE); in dfll_set_force_output_enabled()
642 dfll_wmb(td); in dfll_set_force_output_enabled()
652 static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel) in dfll_force_output() argument
659 val = dfll_set_force_output_value(td, out_sel); in dfll_force_output()
660 if ((td->mode < DFLL_CLOSED_LOOP) && in dfll_force_output()
662 dfll_set_force_output_enabled(td, true); in dfll_force_output()
675 static void dfll_load_i2c_lut(struct tegra_dfll *td) in dfll_load_i2c_lut() argument
681 if (i < td->lut_min) in dfll_load_i2c_lut()
682 lut_index = td->lut_min; in dfll_load_i2c_lut()
683 else if (i > td->lut_max) in dfll_load_i2c_lut()
684 lut_index = td->lut_max; in dfll_load_i2c_lut()
688 val = regulator_list_hardware_vsel(td->vdd_reg, in dfll_load_i2c_lut()
689 td->lut[lut_index]); in dfll_load_i2c_lut()
690 __raw_writel(val, td->lut_base + i * 4); in dfll_load_i2c_lut()
693 dfll_i2c_wmb(td); in dfll_load_i2c_lut()
706 static void dfll_init_i2c_if(struct tegra_dfll *td) in dfll_init_i2c_if() argument
710 if (td->i2c_slave_addr > 0x7f) { in dfll_init_i2c_if()
711 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT; in dfll_init_i2c_if()
714 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT; in dfll_init_i2c_if()
718 dfll_i2c_writel(td, val, DFLL_I2C_CFG); in dfll_init_i2c_if()
720 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR); in dfll_init_i2c_if()
722 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8); in dfll_init_i2c_if()
728 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR); in dfll_init_i2c_if()
729 dfll_i2c_wmb(td); in dfll_init_i2c_if()
740 static void dfll_init_out_if(struct tegra_dfll *td) in dfll_init_out_if() argument
744 td->lut_min = td->lut_bottom; in dfll_init_out_if()
745 td->lut_max = td->lut_size - 1; in dfll_init_out_if()
746 td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0); in dfll_init_out_if()
749 dfll_writel(td, 0, DFLL_OUTPUT_CFG); in dfll_init_out_if()
750 dfll_wmb(td); in dfll_init_out_if()
752 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | in dfll_init_out_if()
753 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | in dfll_init_out_if()
754 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); in dfll_init_out_if()
755 dfll_writel(td, val, DFLL_OUTPUT_CFG); in dfll_init_out_if()
756 dfll_wmb(td); in dfll_init_out_if()
758 dfll_writel(td, 0, DFLL_OUTPUT_FORCE); in dfll_init_out_if()
759 dfll_i2c_writel(td, 0, DFLL_INTR_EN); in dfll_init_out_if()
760 dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK, in dfll_init_out_if()
763 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) { in dfll_init_out_if()
764 u32 vinit = td->reg_init_uV; in dfll_init_out_if()
765 int vstep = td->soc->alignment.step_uv; in dfll_init_out_if()
766 unsigned long vmin = td->lut_uv[0]; in dfll_init_out_if()
773 dfll_force_output(td, vsel); in dfll_init_out_if()
776 dfll_load_i2c_lut(td); in dfll_init_out_if()
777 dfll_init_i2c_if(td); in dfll_init_out_if()
795 static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) in find_lut_index_for_rate() argument
800 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in find_lut_index_for_rate()
804 align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv; in find_lut_index_for_rate()
807 for (i = td->lut_bottom; i < td->lut_size; i++) { in find_lut_index_for_rate()
808 if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step) in find_lut_index_for_rate()
826 static int dfll_calculate_rate_request(struct tegra_dfll *td, in dfll_calculate_rate_request() argument
839 if (rate < td->dvco_rate_min) { in dfll_calculate_rate_request()
843 td->dvco_rate_min / 1000); in dfll_calculate_rate_request()
845 dev_err(td->dev, "%s: Rate %lu is too low\n", in dfll_calculate_rate_request()
850 rate = td->dvco_rate_min; in dfll_calculate_rate_request()
854 val = DVCO_RATE_TO_MULT(rate, td->ref_rate); in dfll_calculate_rate_request()
856 dev_err(td->dev, "%s: Rate %lu is above dfll range\n", in dfll_calculate_rate_request()
861 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate); in dfll_calculate_rate_request()
864 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate); in dfll_calculate_rate_request()
879 static void dfll_set_frequency_request(struct tegra_dfll *td, in dfll_set_frequency_request() argument
886 force_val = (req->lut_index - td->lut_safe) * coef / td->cg; in dfll_set_frequency_request()
895 dfll_writel(td, val, DFLL_FREQ_REQ); in dfll_set_frequency_request()
896 dfll_wmb(td); in dfll_set_frequency_request()
911 static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate) in dfll_request_rate() argument
916 if (td->mode == DFLL_UNINITIALIZED) { in dfll_request_rate()
917 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n", in dfll_request_rate()
918 __func__, mode_name[td->mode]); in dfll_request_rate()
922 ret = dfll_calculate_rate_request(td, &req, rate); in dfll_request_rate()
926 td->last_unrounded_rate = rate; in dfll_request_rate()
927 td->last_req = req; in dfll_request_rate()
929 if (td->mode == DFLL_CLOSED_LOOP) in dfll_request_rate()
930 dfll_set_frequency_request(td, &td->last_req); in dfll_request_rate()
946 static int dfll_disable(struct tegra_dfll *td) in dfll_disable() argument
948 if (td->mode != DFLL_OPEN_LOOP) { in dfll_disable()
949 dev_err(td->dev, "cannot disable DFLL in %s mode\n", in dfll_disable()
950 mode_name[td->mode]); in dfll_disable()
954 dfll_set_mode(td, DFLL_DISABLED); in dfll_disable()
955 pm_runtime_put_sync(td->dev); in dfll_disable()
967 static int dfll_enable(struct tegra_dfll *td) in dfll_enable() argument
969 if (td->mode != DFLL_DISABLED) { in dfll_enable()
970 dev_err(td->dev, "cannot enable DFLL in %s mode\n", in dfll_enable()
971 mode_name[td->mode]); in dfll_enable()
975 pm_runtime_get_sync(td->dev); in dfll_enable()
976 dfll_set_mode(td, DFLL_OPEN_LOOP); in dfll_enable()
992 static void dfll_set_open_loop_config(struct tegra_dfll *td) in dfll_set_open_loop_config() argument
997 if (td->tune_range != DFLL_TUNE_LOW) in dfll_set_open_loop_config()
998 dfll_tune_low(td); in dfll_set_open_loop_config()
1000 val = dfll_readl(td, DFLL_FREQ_REQ); in dfll_set_open_loop_config()
1003 dfll_writel(td, val, DFLL_FREQ_REQ); in dfll_set_open_loop_config()
1004 dfll_wmb(td); in dfll_set_open_loop_config()
1015 static int dfll_lock(struct tegra_dfll *td) in dfll_lock() argument
1017 struct dfll_rate_req *req = &td->last_req; in dfll_lock()
1019 switch (td->mode) { in dfll_lock()
1025 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n", in dfll_lock()
1030 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) in dfll_lock()
1031 dfll_pwm_set_output_enabled(td, true); in dfll_lock()
1033 dfll_i2c_set_output_enabled(td, true); in dfll_lock()
1035 dfll_set_mode(td, DFLL_CLOSED_LOOP); in dfll_lock()
1036 dfll_set_frequency_request(td, req); in dfll_lock()
1037 dfll_set_force_output_enabled(td, false); in dfll_lock()
1041 BUG_ON(td->mode > DFLL_CLOSED_LOOP); in dfll_lock()
1042 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n", in dfll_lock()
1043 __func__, mode_name[td->mode]); in dfll_lock()
1055 static int dfll_unlock(struct tegra_dfll *td) in dfll_unlock() argument
1057 switch (td->mode) { in dfll_unlock()
1059 dfll_set_open_loop_config(td); in dfll_unlock()
1060 dfll_set_mode(td, DFLL_OPEN_LOOP); in dfll_unlock()
1061 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) in dfll_unlock()
1062 dfll_pwm_set_output_enabled(td, false); in dfll_unlock()
1064 dfll_i2c_set_output_enabled(td, false); in dfll_unlock()
1071 BUG_ON(td->mode > DFLL_CLOSED_LOOP); in dfll_unlock()
1072 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n", in dfll_unlock()
1073 __func__, mode_name[td->mode]); in dfll_unlock()
1089 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_is_enabled() local
1091 return dfll_is_running(td); in dfll_clk_is_enabled()
1096 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_enable() local
1099 ret = dfll_enable(td); in dfll_clk_enable()
1103 ret = dfll_lock(td); in dfll_clk_enable()
1105 dfll_disable(td); in dfll_clk_enable()
1112 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_disable() local
1115 ret = dfll_unlock(td); in dfll_clk_disable()
1117 dfll_disable(td); in dfll_clk_disable()
1123 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_recalc_rate() local
1125 return td->last_unrounded_rate; in dfll_clk_recalc_rate()
1132 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_determine_rate() local
1136 ret = dfll_calculate_rate_request(td, &req, clk_req->rate); in dfll_clk_determine_rate()
1152 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_set_rate() local
1154 return dfll_request_rate(td, rate); in dfll_clk_set_rate()
1179 static int dfll_register_clk(struct tegra_dfll *td) in dfll_register_clk() argument
1183 dfll_clk_init_data.name = td->output_clock_name; in dfll_register_clk()
1184 td->dfll_clk_hw.init = &dfll_clk_init_data; in dfll_register_clk()
1186 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw); in dfll_register_clk()
1187 if (IS_ERR(td->dfll_clk)) { in dfll_register_clk()
1188 dev_err(td->dev, "DFLL clock registration error\n"); in dfll_register_clk()
1192 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get, in dfll_register_clk()
1193 td->dfll_clk); in dfll_register_clk()
1195 dev_err(td->dev, "of_clk_add_provider() failed\n"); in dfll_register_clk()
1197 clk_unregister(td->dfll_clk); in dfll_register_clk()
1211 static void dfll_unregister_clk(struct tegra_dfll *td) in dfll_unregister_clk() argument
1213 of_clk_del_provider(td->dev->of_node); in dfll_unregister_clk()
1214 clk_unregister(td->dfll_clk); in dfll_unregister_clk()
1215 td->dfll_clk = NULL; in dfll_unregister_clk()
1254 static u64 dfll_read_monitor_rate(struct tegra_dfll *td) in dfll_read_monitor_rate() argument
1259 if (!dfll_is_running(td)) in dfll_read_monitor_rate()
1262 v = dfll_readl(td, DFLL_MONITOR_DATA); in dfll_read_monitor_rate()
1264 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate); in dfll_read_monitor_rate()
1266 s = dfll_readl(td, DFLL_FREQ_REQ); in dfll_read_monitor_rate()
1275 struct tegra_dfll *td = data; in attr_enable_get() local
1277 *val = dfll_is_running(td); in attr_enable_get()
1283 struct tegra_dfll *td = data; in attr_enable_set() local
1285 return val ? dfll_enable(td) : dfll_disable(td); in attr_enable_set()
1292 struct tegra_dfll *td = data; in attr_lock_get() local
1294 *val = (td->mode == DFLL_CLOSED_LOOP); in attr_lock_get()
1300 struct tegra_dfll *td = data; in attr_lock_set() local
1302 return val ? dfll_lock(td) : dfll_unlock(td); in attr_lock_set()
1308 struct tegra_dfll *td = data; in attr_rate_get() local
1310 *val = dfll_read_monitor_rate(td); in attr_rate_get()
1317 struct tegra_dfll *td = data; in attr_rate_set() local
1319 return dfll_request_rate(td, val); in attr_rate_set()
1326 struct tegra_dfll *td = s->private; in attr_registers_show() local
1331 val = dfll_i2c_readl(td, offs); in attr_registers_show()
1333 val = dfll_readl(td, offs); in attr_registers_show()
1340 dfll_i2c_readl(td, offs)); in attr_registers_show()
1343 dfll_i2c_readl(td, offs)); in attr_registers_show()
1345 if (td->pmu_if == TEGRA_DFLL_PMU_I2C) { in attr_registers_show()
1349 __raw_readl(td->i2c_controller_base + offs)); in attr_registers_show()
1354 __raw_readl(td->lut_base + offs)); in attr_registers_show()
1362 static void dfll_debug_init(struct tegra_dfll *td) in dfll_debug_init() argument
1366 if (!td || (td->mode == DFLL_UNINITIALIZED)) in dfll_debug_init()
1370 td->debugfs_dir = root; in dfll_debug_init()
1372 debugfs_create_file_unsafe("enable", 0644, root, td, in dfll_debug_init()
1374 debugfs_create_file_unsafe("lock", 0444, root, td, &lock_fops); in dfll_debug_init()
1375 debugfs_create_file_unsafe("rate", 0444, root, td, &rate_fops); in dfll_debug_init()
1376 debugfs_create_file("registers", 0444, root, td, &attr_registers_fops); in dfll_debug_init()
1380 static inline void dfll_debug_init(struct tegra_dfll *td) { } in dfll_debug_init() argument
1395 static void dfll_set_default_params(struct tegra_dfll *td) in dfll_set_default_params() argument
1399 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32); in dfll_set_default_params()
1401 dfll_writel(td, val, DFLL_CONFIG); in dfll_set_default_params()
1403 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) | in dfll_set_default_params()
1404 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) | in dfll_set_default_params()
1405 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) | in dfll_set_default_params()
1406 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) | in dfll_set_default_params()
1407 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0); in dfll_set_default_params()
1408 dfll_writel(td, val, DFLL_PARAMS); in dfll_set_default_params()
1410 dfll_tune_low(td); in dfll_set_default_params()
1411 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL); in dfll_set_default_params()
1412 dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL); in dfll_set_default_params()
1423 static int dfll_init_clks(struct tegra_dfll *td) in dfll_init_clks() argument
1425 td->ref_clk = devm_clk_get(td->dev, "ref"); in dfll_init_clks()
1426 if (IS_ERR(td->ref_clk)) { in dfll_init_clks()
1427 dev_err(td->dev, "missing ref clock\n"); in dfll_init_clks()
1428 return PTR_ERR(td->ref_clk); in dfll_init_clks()
1431 td->soc_clk = devm_clk_get(td->dev, "soc"); in dfll_init_clks()
1432 if (IS_ERR(td->soc_clk)) { in dfll_init_clks()
1433 dev_err(td->dev, "missing soc clock\n"); in dfll_init_clks()
1434 return PTR_ERR(td->soc_clk); in dfll_init_clks()
1437 td->i2c_clk = devm_clk_get(td->dev, "i2c"); in dfll_init_clks()
1438 if (IS_ERR(td->i2c_clk)) { in dfll_init_clks()
1439 dev_err(td->dev, "missing i2c clock\n"); in dfll_init_clks()
1440 return PTR_ERR(td->i2c_clk); in dfll_init_clks()
1442 td->i2c_clk_rate = clk_get_rate(td->i2c_clk); in dfll_init_clks()
1456 static int dfll_init(struct tegra_dfll *td) in dfll_init() argument
1460 td->ref_rate = clk_get_rate(td->ref_clk); in dfll_init()
1461 if (td->ref_rate != REF_CLOCK_RATE) { in dfll_init()
1462 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu", in dfll_init()
1463 td->ref_rate, REF_CLOCK_RATE); in dfll_init()
1467 reset_control_deassert(td->dvco_rst); in dfll_init()
1469 ret = clk_prepare(td->ref_clk); in dfll_init()
1471 dev_err(td->dev, "failed to prepare ref_clk\n"); in dfll_init()
1475 ret = clk_prepare(td->soc_clk); in dfll_init()
1477 dev_err(td->dev, "failed to prepare soc_clk\n"); in dfll_init()
1481 ret = clk_prepare(td->i2c_clk); in dfll_init()
1483 dev_err(td->dev, "failed to prepare i2c_clk\n"); in dfll_init()
1487 td->last_unrounded_rate = 0; in dfll_init()
1489 pm_runtime_enable(td->dev); in dfll_init()
1490 pm_runtime_get_sync(td->dev); in dfll_init()
1492 dfll_set_mode(td, DFLL_DISABLED); in dfll_init()
1493 dfll_set_default_params(td); in dfll_init()
1495 if (td->soc->init_clock_trimmers) in dfll_init()
1496 td->soc->init_clock_trimmers(); in dfll_init()
1498 dfll_set_open_loop_config(td); in dfll_init()
1500 dfll_init_out_if(td); in dfll_init()
1502 pm_runtime_put_sync(td->dev); in dfll_init()
1507 clk_unprepare(td->soc_clk); in dfll_init()
1509 clk_unprepare(td->ref_clk); in dfll_init()
1511 reset_control_assert(td->dvco_rst); in dfll_init()
1525 struct tegra_dfll *td = dev_get_drvdata(dev); in tegra_dfll_suspend() local
1527 if (dfll_is_running(td)) { in tegra_dfll_suspend()
1528 dev_err(td->dev, "DFLL still enabled while suspending\n"); in tegra_dfll_suspend()
1532 reset_control_assert(td->dvco_rst); in tegra_dfll_suspend()
1549 struct tegra_dfll *td = dev_get_drvdata(dev); in tegra_dfll_resume() local
1551 reset_control_deassert(td->dvco_rst); in tegra_dfll_resume()
1553 pm_runtime_get_sync(td->dev); in tegra_dfll_resume()
1555 dfll_set_mode(td, DFLL_DISABLED); in tegra_dfll_resume()
1556 dfll_set_default_params(td); in tegra_dfll_resume()
1558 if (td->soc->init_clock_trimmers) in tegra_dfll_resume()
1559 td->soc->init_clock_trimmers(); in tegra_dfll_resume()
1561 dfll_set_open_loop_config(td); in tegra_dfll_resume()
1563 dfll_init_out_if(td); in tegra_dfll_resume()
1565 pm_runtime_put_sync(td->dev); in tegra_dfll_resume()
1579 static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) in find_vdd_map_entry_exact() argument
1583 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM)) in find_vdd_map_entry_exact()
1586 align_step = uV / td->soc->alignment.step_uv; in find_vdd_map_entry_exact()
1587 n_voltages = regulator_count_voltages(td->vdd_reg); in find_vdd_map_entry_exact()
1589 reg_uV = regulator_list_voltage(td->vdd_reg, i); in find_vdd_map_entry_exact()
1593 reg_volt_id = reg_uV / td->soc->alignment.step_uv; in find_vdd_map_entry_exact()
1599 dev_err(td->dev, "no voltage map entry for %d uV\n", uV); in find_vdd_map_entry_exact()
1607 static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) in find_vdd_map_entry_min() argument
1611 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM)) in find_vdd_map_entry_min()
1614 align_step = uV / td->soc->alignment.step_uv; in find_vdd_map_entry_min()
1615 n_voltages = regulator_count_voltages(td->vdd_reg); in find_vdd_map_entry_min()
1617 reg_uV = regulator_list_voltage(td->vdd_reg, i); in find_vdd_map_entry_min()
1621 reg_volt_id = reg_uV / td->soc->alignment.step_uv; in find_vdd_map_entry_min()
1627 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV); in find_vdd_map_entry_min()
1640 static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max) in dfll_build_pwm_lut() argument
1645 int v_min = td->soc->cvb->min_millivolts * 1000; in dfll_build_pwm_lut()
1648 reg_volt = td->lut_uv[i]; in dfll_build_pwm_lut()
1655 td->lut[i] = i; in dfll_build_pwm_lut()
1661 td->lut_size = i; in dfll_build_pwm_lut()
1663 (lut_bottom + 1 >= td->lut_size)) { in dfll_build_pwm_lut()
1664 dev_err(td->dev, "no voltage above DFLL minimum %d mV\n", in dfll_build_pwm_lut()
1665 td->soc->cvb->min_millivolts); in dfll_build_pwm_lut()
1668 td->lut_bottom = lut_bottom; in dfll_build_pwm_lut()
1671 rate = get_dvco_rate_below(td, td->lut_bottom); in dfll_build_pwm_lut()
1673 dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n", in dfll_build_pwm_lut()
1674 td->soc->cvb->min_millivolts); in dfll_build_pwm_lut()
1677 td->dvco_rate_min = rate; in dfll_build_pwm_lut()
1695 static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max) in dfll_build_i2c_lut() argument
1701 v = td->soc->cvb->min_millivolts * 1000; in dfll_build_i2c_lut()
1702 lut = find_vdd_map_entry_exact(td, v); in dfll_build_i2c_lut()
1705 td->lut[0] = lut; in dfll_build_i2c_lut()
1706 td->lut_bottom = 0; in dfll_build_i2c_lut()
1711 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in dfll_build_i2c_lut()
1716 if (v_opp <= td->soc->cvb->min_millivolts * 1000) in dfll_build_i2c_lut()
1717 td->dvco_rate_min = dev_pm_opp_get_freq(opp); in dfll_build_i2c_lut()
1726 selector = find_vdd_map_entry_min(td, v); in dfll_build_i2c_lut()
1729 if (selector != td->lut[j - 1]) in dfll_build_i2c_lut()
1730 td->lut[j++] = selector; in dfll_build_i2c_lut()
1734 selector = find_vdd_map_entry_exact(td, v); in dfll_build_i2c_lut()
1737 if (selector != td->lut[j - 1]) in dfll_build_i2c_lut()
1738 td->lut[j++] = selector; in dfll_build_i2c_lut()
1743 td->lut_size = j; in dfll_build_i2c_lut()
1745 if (!td->dvco_rate_min) in dfll_build_i2c_lut()
1746 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n", in dfll_build_i2c_lut()
1747 td->soc->cvb->min_millivolts); in dfll_build_i2c_lut()
1750 for (j = 0; j < td->lut_size; j++) in dfll_build_i2c_lut()
1751 td->lut_uv[j] = in dfll_build_i2c_lut()
1752 regulator_list_voltage(td->vdd_reg, in dfll_build_i2c_lut()
1753 td->lut[j]); in dfll_build_i2c_lut()
1760 static int dfll_build_lut(struct tegra_dfll *td) in dfll_build_lut() argument
1766 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); in dfll_build_lut()
1768 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n"); in dfll_build_lut()
1774 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) in dfll_build_lut()
1775 return dfll_build_pwm_lut(td, v_max); in dfll_build_lut()
1777 return dfll_build_i2c_lut(td, v_max); in dfll_build_lut()
1790 static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest) in read_dt_param() argument
1792 int err = of_property_read_u32(td->dev->of_node, param, dest); in read_dt_param()
1795 dev_err(td->dev, "failed to read DT parameter %s: %d\n", in read_dt_param()
1811 static int dfll_fetch_i2c_params(struct tegra_dfll *td) in dfll_fetch_i2c_params() argument
1819 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate)) in dfll_fetch_i2c_params()
1822 regmap = regulator_get_regmap(td->vdd_reg); in dfll_fetch_i2c_params()
1826 td->i2c_slave_addr = i2c_client->addr; in dfll_fetch_i2c_params()
1828 ret = regulator_get_hardware_vsel_register(td->vdd_reg, in dfll_fetch_i2c_params()
1832 dev_err(td->dev, in dfll_fetch_i2c_params()
1836 td->i2c_reg = vsel_reg; in dfll_fetch_i2c_params()
1841 static int dfll_fetch_pwm_params(struct tegra_dfll *td) in dfll_fetch_pwm_params() argument
1846 if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) { in dfll_fetch_pwm_params()
1847 dev_err(td->dev, in dfll_fetch_pwm_params()
1852 td->lut_uv[i] = td->soc->alignment.offset_uv + in dfll_fetch_pwm_params()
1853 i * td->soc->alignment.step_uv; in dfll_fetch_pwm_params()
1855 ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts", in dfll_fetch_pwm_params()
1856 &td->reg_init_uV); in dfll_fetch_pwm_params()
1858 dev_err(td->dev, "couldn't get initialized voltage\n"); in dfll_fetch_pwm_params()
1862 ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period); in dfll_fetch_pwm_params()
1864 dev_err(td->dev, "couldn't get PWM period\n"); in dfll_fetch_pwm_params()
1867 td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1); in dfll_fetch_pwm_params()
1869 td->pwm_pin = devm_pinctrl_get(td->dev); in dfll_fetch_pwm_params()
1870 if (IS_ERR(td->pwm_pin)) { in dfll_fetch_pwm_params()
1871 dev_err(td->dev, "DT: missing pinctrl device\n"); in dfll_fetch_pwm_params()
1872 return PTR_ERR(td->pwm_pin); in dfll_fetch_pwm_params()
1875 td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin, in dfll_fetch_pwm_params()
1877 if (IS_ERR(td->pwm_enable_state)) { in dfll_fetch_pwm_params()
1878 dev_err(td->dev, "DT: missing pwm enabled state\n"); in dfll_fetch_pwm_params()
1879 return PTR_ERR(td->pwm_enable_state); in dfll_fetch_pwm_params()
1882 td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin, in dfll_fetch_pwm_params()
1884 if (IS_ERR(td->pwm_disable_state)) { in dfll_fetch_pwm_params()
1885 dev_err(td->dev, "DT: missing pwm disabled state\n"); in dfll_fetch_pwm_params()
1886 return PTR_ERR(td->pwm_disable_state); in dfll_fetch_pwm_params()
1899 static int dfll_fetch_common_params(struct tegra_dfll *td) in dfll_fetch_common_params() argument
1903 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl); in dfll_fetch_common_params()
1904 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate); in dfll_fetch_common_params()
1905 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode); in dfll_fetch_common_params()
1906 ok &= read_dt_param(td, "nvidia,cf", &td->cf); in dfll_fetch_common_params()
1907 ok &= read_dt_param(td, "nvidia,ci", &td->ci); in dfll_fetch_common_params()
1908 ok &= read_dt_param(td, "nvidia,cg", &td->cg); in dfll_fetch_common_params()
1909 td->cg_scale = of_property_read_bool(td->dev->of_node, in dfll_fetch_common_params()
1912 if (of_property_read_string(td->dev->of_node, "clock-output-names", in dfll_fetch_common_params()
1913 &td->output_clock_name)) { in dfll_fetch_common_params()
1914 dev_err(td->dev, "missing clock-output-names property\n"); in dfll_fetch_common_params()
1938 struct tegra_dfll *td; in tegra_dfll_register() local
1946 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL); in tegra_dfll_register()
1947 if (!td) in tegra_dfll_register()
1949 td->dev = &pdev->dev; in tegra_dfll_register()
1950 platform_set_drvdata(pdev, td); in tegra_dfll_register()
1952 td->soc = soc; in tegra_dfll_register()
1954 td->dvco_rst = devm_reset_control_get(td->dev, "dvco"); in tegra_dfll_register()
1955 if (IS_ERR(td->dvco_rst)) { in tegra_dfll_register()
1956 dev_err(td->dev, "couldn't get dvco reset\n"); in tegra_dfll_register()
1957 return PTR_ERR(td->dvco_rst); in tegra_dfll_register()
1960 ret = dfll_fetch_common_params(td); in tegra_dfll_register()
1962 dev_err(td->dev, "couldn't parse device tree parameters\n"); in tegra_dfll_register()
1966 if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) { in tegra_dfll_register()
1967 td->pmu_if = TEGRA_DFLL_PMU_PWM; in tegra_dfll_register()
1968 ret = dfll_fetch_pwm_params(td); in tegra_dfll_register()
1970 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu"); in tegra_dfll_register()
1971 if (IS_ERR(td->vdd_reg)) { in tegra_dfll_register()
1972 dev_err(td->dev, "couldn't get vdd_cpu regulator\n"); in tegra_dfll_register()
1973 return PTR_ERR(td->vdd_reg); in tegra_dfll_register()
1975 td->pmu_if = TEGRA_DFLL_PMU_I2C; in tegra_dfll_register()
1976 ret = dfll_fetch_i2c_params(td); in tegra_dfll_register()
1981 ret = dfll_build_lut(td); in tegra_dfll_register()
1983 dev_err(td->dev, "couldn't build LUT\n"); in tegra_dfll_register()
1989 dev_err(td->dev, "no control register resource\n"); in tegra_dfll_register()
1993 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
1994 if (!td->base) { in tegra_dfll_register()
1995 dev_err(td->dev, "couldn't ioremap DFLL control registers\n"); in tegra_dfll_register()
2001 dev_err(td->dev, "no i2c_base resource\n"); in tegra_dfll_register()
2005 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
2006 if (!td->i2c_base) { in tegra_dfll_register()
2007 dev_err(td->dev, "couldn't ioremap i2c_base resource\n"); in tegra_dfll_register()
2013 dev_err(td->dev, "no i2c_controller_base resource\n"); in tegra_dfll_register()
2017 td->i2c_controller_base = devm_ioremap(td->dev, mem->start, in tegra_dfll_register()
2019 if (!td->i2c_controller_base) { in tegra_dfll_register()
2020 dev_err(td->dev, in tegra_dfll_register()
2027 dev_err(td->dev, "no lut_base resource\n"); in tegra_dfll_register()
2031 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
2032 if (!td->lut_base) { in tegra_dfll_register()
2033 dev_err(td->dev, in tegra_dfll_register()
2038 ret = dfll_init_clks(td); in tegra_dfll_register()
2045 ret = dfll_init(td); in tegra_dfll_register()
2049 ret = dfll_register_clk(td); in tegra_dfll_register()
2055 dfll_debug_init(td); in tegra_dfll_register()
2071 struct tegra_dfll *td = platform_get_drvdata(pdev); in tegra_dfll_unregister() local
2074 if (td->mode != DFLL_DISABLED) { in tegra_dfll_unregister()
2080 debugfs_remove_recursive(td->debugfs_dir); in tegra_dfll_unregister()
2082 dfll_unregister_clk(td); in tegra_dfll_unregister()
2085 clk_unprepare(td->ref_clk); in tegra_dfll_unregister()
2086 clk_unprepare(td->soc_clk); in tegra_dfll_unregister()
2087 clk_unprepare(td->i2c_clk); in tegra_dfll_unregister()
2089 reset_control_assert(td->dvco_rst); in tegra_dfll_unregister()
2091 return td->soc; in tegra_dfll_unregister()