Lines Matching refs:present
515 [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true },
516 [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true },
517 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
518 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
519 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
520 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
521 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
522 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
523 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
524 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
525 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
526 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
527 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
528 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
529 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
530 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
531 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
532 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
533 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
534 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
535 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
536 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
537 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
538 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
539 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
540 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
541 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
542 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
543 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
544 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
545 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
546 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
547 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
548 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
549 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
550 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
551 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
552 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
553 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
554 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
555 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
556 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
557 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
558 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
559 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
560 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
561 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
562 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
563 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
564 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
565 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
566 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
567 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },