Lines Matching refs:DT_CLK
731 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
732 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
733 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
734 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
735 DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
736 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
737 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
738 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
739 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
740 DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
741 DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
742 DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
743 DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
744 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
745 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
746 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
747 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
748 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
749 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
750 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
751 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
752 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
753 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
754 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
755 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
756 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
757 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
758 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
759 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
760 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
761 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
762 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
763 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
764 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
765 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
766 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
767 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
768 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
769 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
770 DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
771 DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
772 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
773 DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
774 DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
775 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
776 DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
777 DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
778 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
779 DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
780 DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
781 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
782 DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
783 DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
784 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
785 DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
786 DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
787 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
788 DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
789 DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
790 DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
791 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
792 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
793 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
794 DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
795 DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
796 DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
797 DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
798 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
799 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
800 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
801 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
802 DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
803 DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
804 DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
805 DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
806 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
807 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
808 DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
809 DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
810 DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
811 DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
812 DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
813 DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
814 DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
815 DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
816 DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
817 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
818 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),