Lines Matching refs:DT_CLK
852 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
853 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
854 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
855 DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
856 DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
857 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
858 DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
859 DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
860 DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
861 DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
862 DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
863 DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
864 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
865 DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
866 DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
867 DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
868 DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
869 DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
870 DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
871 DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
872 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
873 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
874 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
875 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
876 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
877 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
878 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
879 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
880 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
881 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
882 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
883 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
884 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
885 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
886 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
887 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
888 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
889 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
890 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
891 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
892 DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
893 DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
894 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
895 DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
896 DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
897 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
898 DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
899 DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
900 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
901 DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
902 DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
903 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
904 DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
905 DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
906 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
907 DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
908 DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
909 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
910 DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
911 DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
912 DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
913 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
914 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
915 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
916 DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
917 DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
918 DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
919 DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
920 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
921 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
922 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
923 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
924 DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
925 DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
926 DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
927 DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
928 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
929 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
930 DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
931 DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
932 DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
933 DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
934 DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
935 DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
936 DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
937 DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
938 DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
939 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
940 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),