Lines Matching refs:clk_hw
20 struct clk_hw hw;
35 struct clk_hw hw;
213 struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
215 struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
222 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
232 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
256 int omap2_init_clk_clkdm(struct clk_hw *hw);
257 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
258 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
260 int omap2_dflt_clk_enable(struct clk_hw *hw);
261 void omap2_dflt_clk_disable(struct clk_hw *hw);
262 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
273 u8 omap2_init_dpll_parent(struct clk_hw *hw);
274 int omap3_noncore_dpll_enable(struct clk_hw *hw);
275 void omap3_noncore_dpll_disable(struct clk_hw *hw);
276 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
277 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
279 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
283 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
285 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
287 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
297 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
298 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
300 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
302 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
306 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
308 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
311 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,