Lines Matching refs:CLK_DIVIDER_ALLOW_ZERO
139 CLK_DIVIDER_ALLOW_ZERO, fclk_lock); in zynq_clk_register_fclk()
143 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_register_fclk()
194 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); in zynq_clk_register_periph_clk()
282 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); in zynq_clk_setup()
326 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); in zynq_clk_setup()
332 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); in zynq_clk_setup()
339 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); in zynq_clk_setup()
342 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
390 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); in zynq_clk_setup()
393 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
415 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); in zynq_clk_setup()
418 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
447 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); in zynq_clk_setup()
450 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
487 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); in zynq_clk_setup()