Lines Matching refs:CLK_DIVIDER_ONE_BASED
138 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_register_fclk()
143 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_register_fclk()
194 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); in zynq_clk_register_periph_clk()
281 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
325 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
331 SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
338 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
342 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
389 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
393 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
414 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
418 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
446 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
450 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
486 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()