Lines Matching refs:io_base
326 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
335 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
347 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
349 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
351 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, in sec_open_sva_prefetch()
366 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
368 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
370 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, in sec_close_sva_prefetch()
384 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
386 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
388 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG); in sec_enable_clock_gate()
390 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG); in sec_enable_clock_gate()
392 val = readl(qm->io_base + SEC_CORE_AUTO_GATE); in sec_enable_clock_gate()
394 writel(val, qm->io_base + SEC_CORE_AUTO_GATE); in sec_enable_clock_gate()
402 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
404 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
415 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); in sec_engine_init()
417 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, in sec_engine_init()
425 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
427 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
429 reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL0_REG); in sec_engine_init()
431 writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL0_REG); in sec_engine_init()
433 reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL1_REG); in sec_engine_init()
439 writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL1_REG); in sec_engine_init()
442 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); in sec_engine_init()
444 writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG); in sec_engine_init()
448 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); in sec_engine_init()
451 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); in sec_engine_init()
453 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); in sec_engine_init()
466 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); in sec_set_user_domain_and_cache()
467 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
468 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); in sec_set_user_domain_and_cache()
469 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
470 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
473 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); in sec_set_user_domain_and_cache()
474 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
477 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); in sec_set_user_domain_and_cache()
478 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); in sec_set_user_domain_and_cache()
483 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL); in sec_set_user_domain_and_cache()
494 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
496 readl(qm->io_base + sec_dfx_regs[i].offset); in sec_debug_regs_clear()
499 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
508 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
518 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL); in sec_master_ooo_ctrl()
520 writel(val1, qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
526 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_enable()
532 writel(SEC_CORE_INT_CLEAR, qm->io_base + SEC_CORE_INT_SOURCE); in sec_hw_error_enable()
535 writel(SEC_RAS_CE_ENB_MSK, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_enable()
536 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); in sec_hw_error_enable()
537 writel(SEC_RAS_NFE_ENB_MSK, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_enable()
543 writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_enable()
549 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_disable()
555 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_disable()
556 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG); in sec_hw_error_disable()
557 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_disable()
562 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & in sec_clear_enable_read()
573 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & in sec_clear_enable_write()
575 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_clear_enable_write()
717 regset->base = qm->io_base; in sec_core_debug_init()
793 err_val = readl(qm->io_base + in sec_log_hw_error()
806 return readl(qm->io_base + SEC_CORE_INT_STATUS); in sec_get_hw_err_status()
811 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE); in sec_clear_hw_err_status()
818 val = readl(qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
819 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
820 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()