Lines Matching refs:io_base
294 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
296 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
298 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, in hisi_zip_open_sva_prefetch()
313 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
315 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
317 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, in hisi_zip_close_sva_prefetch()
331 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); in hisi_zip_enable_clock_gate()
333 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); in hisi_zip_enable_clock_gate()
335 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); in hisi_zip_enable_clock_gate()
337 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); in hisi_zip_enable_clock_gate()
342 void __iomem *base = qm->io_base; in hisi_zip_set_user_domain_and_cache()
396 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_master_ooo_ctrl()
406 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); in hisi_zip_master_ooo_ctrl()
408 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_master_ooo_ctrl()
415 qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
421 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE); in hisi_zip_hw_error_enable()
425 qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); in hisi_zip_hw_error_enable()
426 writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); in hisi_zip_hw_error_enable()
428 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_hw_error_enable()
434 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
440 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_disable()
455 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & in clear_enable_read()
466 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & in clear_enable_write()
468 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in clear_enable_write()
611 regset->base = qm->io_base + core_offsets[i]; in hisi_zip_core_debug_init()
692 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in hisi_zip_debug_regs_clear()
695 readl(qm->io_base + core_offsets[i] + in hisi_zip_debug_regs_clear()
699 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in hisi_zip_debug_regs_clear()
726 err_val = readl(qm->io_base + in hisi_zip_log_hw_error()
739 return readl(qm->io_base + HZIP_CORE_INT_STATUS); in hisi_zip_get_hw_err_status()
744 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); in hisi_zip_clear_hw_err_status()
751 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
754 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
757 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
765 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_close_axi_master_ooo()
767 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_close_axi_master_ooo()
771 qm->io_base + HZIP_CORE_INT_SET); in hisi_zip_close_axi_master_ooo()