Lines Matching refs:csr_val
306 unsigned int csr_val; in qat_hal_reset() local
308 csr_val = GET_CAP_CSR(handle, reset_csr); in qat_hal_reset()
309 csr_val |= reset_mask; in qat_hal_reset()
310 SET_CAP_CSR(handle, reset_csr, csr_val); in qat_hal_reset()
315 unsigned int ae_csr, unsigned int csr_val) in qat_hal_wr_indr_csr() argument
325 qat_hal_wr_ae_csr(handle, ae, ae_csr, csr_val); in qat_hal_wr_indr_csr()
335 unsigned int cur_ctx, csr_val; in qat_hal_rd_indr_csr() local
339 csr_val = qat_hal_rd_ae_csr(handle, ae, ae_csr); in qat_hal_rd_indr_csr()
342 return csr_val; in qat_hal_rd_indr_csr()
447 unsigned int csr_val; in qat_hal_init_esram() local
453 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
454 if ((csr_val & ESRAM_AUTO_TINIT) && (csr_val & ESRAM_AUTO_TINIT_DONE)) in qat_hal_init_esram()
457 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
458 csr_val |= ESRAM_AUTO_TINIT; in qat_hal_init_esram()
459 ADF_CSR_WR(csr_addr, 0, csr_val); in qat_hal_init_esram()
463 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
464 } while (!(csr_val & ESRAM_AUTO_TINIT_DONE) && times--); in qat_hal_init_esram()
481 unsigned int csr_val; in qat_hal_clr_reset() local
484 csr_val = GET_CAP_CSR(handle, reset_csr); in qat_hal_clr_reset()
485 csr_val &= ~reset_mask; in qat_hal_clr_reset()
487 SET_CAP_CSR(handle, reset_csr, csr_val); in qat_hal_clr_reset()
490 csr_val = GET_CAP_CSR(handle, reset_csr); in qat_hal_clr_reset()
491 csr_val &= reset_mask; in qat_hal_clr_reset()
492 } while (csr_val); in qat_hal_clr_reset()
494 csr_val = GET_CAP_CSR(handle, clk_csr); in qat_hal_clr_reset()
495 csr_val |= reset_mask; in qat_hal_clr_reset()
496 SET_CAP_CSR(handle, clk_csr, csr_val); in qat_hal_clr_reset()
627 unsigned int csr_val = 0; in qat_hal_clear_gpr() local
632 csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL); in qat_hal_clear_gpr()
633 csr_val &= ~(1 << MMC_SHARE_CS_BITPOS); in qat_hal_clear_gpr()
634 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val); in qat_hal_clear_gpr()
635 csr_val = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_clear_gpr()
636 csr_val &= IGNORE_W1C_MASK; in qat_hal_clear_gpr()
638 csr_val |= CE_NN_MODE; in qat_hal_clear_gpr()
640 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val); in qat_hal_clear_gpr()
691 unsigned int csr_val = 0; in qat_hal_chip_init() local
832 csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE); in qat_hal_chip_init()
833 csr_val |= 0x1; in qat_hal_chip_init()
834 qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val); in qat_hal_chip_init()
1013 unsigned int csr_val = 0, newcsr_val; in qat_hal_exec_micro_inst() local
1086 csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL); in qat_hal_exec_micro_inst()
1087 newcsr_val = CLR_BIT(csr_val, MMC_SHARE_CS_BITPOS); in qat_hal_exec_micro_inst()