Lines Matching refs:reg_width
351 u32 reg_width, val; in dw_axi_dma_set_byte_halfword() local
358 reg_width = __ffs(chan->config.dst_addr_width); in dw_axi_dma_set_byte_halfword()
359 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) in dw_axi_dma_set_byte_halfword()
603 unsigned int reg_width; in dw_axi_dma_set_hw_desc() local
624 reg_width = __ffs(chan->config.dst_addr_width); in dw_axi_dma_set_hw_desc()
626 ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS | in dw_axi_dma_set_hw_desc()
633 reg_width = __ffs(chan->config.src_addr_width); in dw_axi_dma_set_hw_desc()
635 ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS | in dw_axi_dma_set_hw_desc()
639 block_ts = len >> reg_width; in dw_axi_dma_set_hw_desc()
687 u32 data_width, reg_width, mem_width; in calculate_block_len() local
702 reg_width = __ffs(chan->config.src_addr_width); in calculate_block_len()
703 block_len = axi_block_ts << reg_width; in calculate_block_len()