Lines Matching refs:eic
54 struct ep93xx_gpio_irq_chip *eic; member
68 return egc->eic; in to_ep93xx_gpio_irq_chip()
83 struct ep93xx_gpio_irq_chip *eic) in ep93xx_gpio_update_int_params() argument
85 writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); in ep93xx_gpio_update_int_params()
87 writeb_relaxed(eic->int_type2, in ep93xx_gpio_update_int_params()
88 epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); in ep93xx_gpio_update_int_params()
90 writeb_relaxed(eic->int_type1, in ep93xx_gpio_update_int_params()
91 epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); in ep93xx_gpio_update_int_params()
93 writeb_relaxed(eic->int_unmasked & eic->int_enabled, in ep93xx_gpio_update_int_params()
94 epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); in ep93xx_gpio_update_int_params()
101 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); in ep93xx_gpio_int_debounce() local
105 eic->int_debounce |= port_mask; in ep93xx_gpio_int_debounce()
107 eic->int_debounce &= ~port_mask; in ep93xx_gpio_int_debounce()
109 writeb(eic->int_debounce, in ep93xx_gpio_int_debounce()
110 epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET); in ep93xx_gpio_int_debounce()
162 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); in ep93xx_gpio_irq_ack() local
167 eic->int_type2 ^= port_mask; /* switch edge direction */ in ep93xx_gpio_irq_ack()
168 ep93xx_gpio_update_int_params(epg, eic); in ep93xx_gpio_irq_ack()
171 writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); in ep93xx_gpio_irq_ack()
177 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); in ep93xx_gpio_irq_mask_ack() local
182 eic->int_type2 ^= port_mask; /* switch edge direction */ in ep93xx_gpio_irq_mask_ack()
184 eic->int_unmasked &= ~port_mask; in ep93xx_gpio_irq_mask_ack()
185 ep93xx_gpio_update_int_params(epg, eic); in ep93xx_gpio_irq_mask_ack()
187 writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); in ep93xx_gpio_irq_mask_ack()
193 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); in ep93xx_gpio_irq_mask() local
196 eic->int_unmasked &= ~BIT(d->irq & 7); in ep93xx_gpio_irq_mask()
197 ep93xx_gpio_update_int_params(epg, eic); in ep93xx_gpio_irq_mask()
203 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); in ep93xx_gpio_irq_unmask() local
206 eic->int_unmasked |= BIT(d->irq & 7); in ep93xx_gpio_irq_unmask()
207 ep93xx_gpio_update_int_params(epg, eic); in ep93xx_gpio_irq_unmask()
218 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); in ep93xx_gpio_irq_type() local
228 eic->int_type1 |= port_mask; in ep93xx_gpio_irq_type()
229 eic->int_type2 |= port_mask; in ep93xx_gpio_irq_type()
233 eic->int_type1 |= port_mask; in ep93xx_gpio_irq_type()
234 eic->int_type2 &= ~port_mask; in ep93xx_gpio_irq_type()
238 eic->int_type1 &= ~port_mask; in ep93xx_gpio_irq_type()
239 eic->int_type2 |= port_mask; in ep93xx_gpio_irq_type()
243 eic->int_type1 &= ~port_mask; in ep93xx_gpio_irq_type()
244 eic->int_type2 &= ~port_mask; in ep93xx_gpio_irq_type()
248 eic->int_type1 |= port_mask; in ep93xx_gpio_irq_type()
251 eic->int_type2 &= ~port_mask; /* falling */ in ep93xx_gpio_irq_type()
253 eic->int_type2 |= port_mask; /* rising */ in ep93xx_gpio_irq_type()
262 eic->int_enabled |= port_mask; in ep93xx_gpio_irq_type()
264 ep93xx_gpio_update_int_params(epg, eic); in ep93xx_gpio_irq_type()
356 egc->eic = devm_kcalloc(dev, 1, in ep93xx_gpio_add_bank()
357 sizeof(*egc->eic), in ep93xx_gpio_add_bank()
359 if (!egc->eic) in ep93xx_gpio_add_bank()
361 egc->eic->irq_offset = bank->irq; in ep93xx_gpio_add_bank()
362 ic = &egc->eic->ic; in ep93xx_gpio_add_bank()