Lines Matching refs:wg
127 static void wcove_update_irq_mask(struct wcove_gpio *wg, irq_hw_number_t gpio) in wcove_update_irq_mask() argument
131 if (wg->set_irq_mask) in wcove_update_irq_mask()
132 regmap_set_bits(wg->regmap, reg, mask); in wcove_update_irq_mask()
134 regmap_clear_bits(wg->regmap, reg, mask); in wcove_update_irq_mask()
137 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, irq_hw_number_t gpio) in wcove_update_irq_ctrl() argument
141 regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt); in wcove_update_irq_ctrl()
146 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_gpio_dir_in() local
152 return regmap_write(wg->regmap, reg, CTLO_INPUT_SET); in wcove_gpio_dir_in()
158 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_gpio_dir_out() local
164 return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value); in wcove_gpio_dir_out()
169 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_gpio_get_direction() local
176 ret = regmap_read(wg->regmap, reg, &val); in wcove_gpio_get_direction()
188 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_gpio_get() local
195 ret = regmap_read(wg->regmap, reg, &val); in wcove_gpio_get()
204 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_gpio_set() local
211 regmap_set_bits(wg->regmap, reg, 1); in wcove_gpio_set()
213 regmap_clear_bits(wg->regmap, reg, 1); in wcove_gpio_set()
219 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_gpio_set_config() local
227 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, in wcove_gpio_set_config()
230 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, in wcove_gpio_set_config()
242 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_irq_type() local
250 wg->intcnt = CTLI_INTCNT_DIS; in wcove_irq_type()
253 wg->intcnt = CTLI_INTCNT_BE; in wcove_irq_type()
256 wg->intcnt = CTLI_INTCNT_PE; in wcove_irq_type()
259 wg->intcnt = CTLI_INTCNT_NE; in wcove_irq_type()
265 wg->update |= UPDATE_IRQ_TYPE; in wcove_irq_type()
273 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_bus_lock() local
275 mutex_lock(&wg->buslock); in wcove_bus_lock()
281 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_bus_sync_unlock() local
284 if (wg->update & UPDATE_IRQ_TYPE) in wcove_bus_sync_unlock()
285 wcove_update_irq_ctrl(wg, gpio); in wcove_bus_sync_unlock()
286 if (wg->update & UPDATE_IRQ_MASK) in wcove_bus_sync_unlock()
287 wcove_update_irq_mask(wg, gpio); in wcove_bus_sync_unlock()
288 wg->update = 0; in wcove_bus_sync_unlock()
290 mutex_unlock(&wg->buslock); in wcove_bus_sync_unlock()
296 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_irq_unmask() local
302 wg->set_irq_mask = false; in wcove_irq_unmask()
303 wg->update |= UPDATE_IRQ_MASK; in wcove_irq_unmask()
309 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_irq_mask() local
315 wg->set_irq_mask = true; in wcove_irq_mask()
316 wg->update |= UPDATE_IRQ_MASK; in wcove_irq_mask()
330 struct wcove_gpio *wg = (struct wcove_gpio *)data; in wcove_gpio_irq_handler() local
335 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { in wcove_gpio_irq_handler()
336 dev_err(wg->dev, "Failed to read irq status register\n"); in wcove_gpio_irq_handler()
350 virq = irq_find_mapping(wg->chip.irq.domain, gpio); in wcove_gpio_irq_handler()
352 regmap_set_bits(wg->regmap, reg, mask); in wcove_gpio_irq_handler()
356 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { in wcove_gpio_irq_handler()
357 dev_err(wg->dev, "Failed to read irq status\n"); in wcove_gpio_irq_handler()
370 struct wcove_gpio *wg = gpiochip_get_data(chip); in wcove_gpio_dbg_show() local
374 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); in wcove_gpio_dbg_show()
375 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli); in wcove_gpio_dbg_show()
377 dev_err(wg->dev, "Failed to read registers: CTRL out/in\n"); in wcove_gpio_dbg_show()
381 ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask); in wcove_gpio_dbg_show()
382 ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status); in wcove_gpio_dbg_show()
384 dev_err(wg->dev, "Failed to read registers: IRQ status/mask\n"); in wcove_gpio_dbg_show()
402 struct wcove_gpio *wg; in wcove_gpio_probe() local
424 wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL); in wcove_gpio_probe()
425 if (!wg) in wcove_gpio_probe()
428 wg->regmap_irq_chip = pmic->irq_chip_data; in wcove_gpio_probe()
430 platform_set_drvdata(pdev, wg); in wcove_gpio_probe()
432 mutex_init(&wg->buslock); in wcove_gpio_probe()
433 wg->chip.label = KBUILD_MODNAME; in wcove_gpio_probe()
434 wg->chip.direction_input = wcove_gpio_dir_in; in wcove_gpio_probe()
435 wg->chip.direction_output = wcove_gpio_dir_out; in wcove_gpio_probe()
436 wg->chip.get_direction = wcove_gpio_get_direction; in wcove_gpio_probe()
437 wg->chip.get = wcove_gpio_get; in wcove_gpio_probe()
438 wg->chip.set = wcove_gpio_set; in wcove_gpio_probe()
439 wg->chip.set_config = wcove_gpio_set_config; in wcove_gpio_probe()
440 wg->chip.base = -1; in wcove_gpio_probe()
441 wg->chip.ngpio = WCOVE_VGPIO_NUM; in wcove_gpio_probe()
442 wg->chip.can_sleep = true; in wcove_gpio_probe()
443 wg->chip.parent = pdev->dev.parent; in wcove_gpio_probe()
444 wg->chip.dbg_show = wcove_gpio_dbg_show; in wcove_gpio_probe()
445 wg->dev = dev; in wcove_gpio_probe()
446 wg->regmap = pmic->regmap; in wcove_gpio_probe()
448 virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq); in wcove_gpio_probe()
454 girq = &wg->chip.irq; in wcove_gpio_probe()
465 IRQF_ONESHOT, pdev->name, wg); in wcove_gpio_probe()
471 ret = devm_gpiochip_add_data(dev, &wg->chip, wg); in wcove_gpio_probe()
478 ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 0, GPIO_IRQ0_MASK); in wcove_gpio_probe()
483 ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK); in wcove_gpio_probe()