Lines Matching defs:amdgpu_crtc
384 struct amdgpu_crtc { struct
385 struct drm_crtc base;
386 int crtc_id;
387 bool enabled;
388 bool can_tile;
389 uint32_t crtc_offset;
390 struct drm_gem_object *cursor_bo;
391 uint64_t cursor_addr;
392 int cursor_x;
393 int cursor_y;
394 int cursor_hot_x;
395 int cursor_hot_y;
396 int cursor_width;
397 int cursor_height;
398 int max_cursor_width;
399 int max_cursor_height;
400 enum amdgpu_rmx_type rmx_type;
401 u8 h_border;
402 u8 v_border;
403 fixed20_12 vsc;
404 fixed20_12 hsc;
405 struct drm_display_mode native_mode;
406 u32 pll_id;
408 struct amdgpu_flip_work *pflip_works;
409 enum amdgpu_flip_status pflip_status;
410 int deferred_flip_completion;
412 struct dm_irq_params dm_irq_params;
414 struct amdgpu_atom_ss ss;
415 bool ss_enabled;
416 u32 adjusted_clock;
417 int bpc;
418 u32 pll_reference_div;
419 u32 pll_post_div;
420 u32 pll_flags;
421 struct drm_encoder *encoder;
422 struct drm_connector *connector;
424 u32 line_time;
425 u32 wm_low;
426 u32 wm_high;
427 u32 lb_vblank_lead_lines;
428 struct drm_display_mode hw_mode;
430 struct hrtimer vblank_timer;
431 enum amdgpu_interrupt_state vsync_timer_enabled;
433 int otg_inst;
434 struct drm_pending_vblank_event *event;