Lines Matching refs:virt
179 adev->virt.fw_reserve.checksum_key = in xgpu_ai_send_access_requests()
247 struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work); in xgpu_ai_mailbox_flr_work() local
248 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); in xgpu_ai_mailbox_flr_work()
305 schedule_work(&adev->virt.flr_work); in xgpu_ai_mailbox_rcv_irq()
336 adev->virt.ack_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
337 adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
338 adev->virt.rcv_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
339 adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
346 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); in xgpu_ai_mailbox_add_irq_id()
350 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_ai_mailbox_add_irq_id()
352 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_add_irq_id()
363 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_get_irq()
366 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_get_irq()
368 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_get_irq()
372 INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work); in xgpu_ai_mailbox_get_irq()
379 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_put_irq()
380 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_put_irq()