Lines Matching refs:virt
186 adev->virt.req_init_data_ver = 0; in xgpu_nv_send_access_requests()
190 adev->virt.req_init_data_ver = in xgpu_nv_send_access_requests()
194 if (adev->virt.req_init_data_ver < 1) in xgpu_nv_send_access_requests()
195 adev->virt.req_init_data_ver = 1; in xgpu_nv_send_access_requests()
201 adev->virt.fw_reserve.checksum_key = in xgpu_nv_send_access_requests()
276 struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work); in xgpu_nv_mailbox_flr_work() local
277 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); in xgpu_nv_mailbox_flr_work()
340 schedule_work(&adev->virt.flr_work); in xgpu_nv_mailbox_rcv_irq()
368 adev->virt.ack_irq.num_types = 1; in xgpu_nv_mailbox_set_irq_funcs()
369 adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs; in xgpu_nv_mailbox_set_irq_funcs()
370 adev->virt.rcv_irq.num_types = 1; in xgpu_nv_mailbox_set_irq_funcs()
371 adev->virt.rcv_irq.funcs = &xgpu_nv_mailbox_rcv_irq_funcs; in xgpu_nv_mailbox_set_irq_funcs()
378 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); in xgpu_nv_mailbox_add_irq_id()
382 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_nv_mailbox_add_irq_id()
384 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_add_irq_id()
395 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_get_irq()
398 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_nv_mailbox_get_irq()
400 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_get_irq()
404 INIT_WORK(&adev->virt.flr_work, xgpu_nv_mailbox_flr_work); in xgpu_nv_mailbox_get_irq()
411 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_nv_mailbox_put_irq()
412 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_put_irq()