Lines Matching refs:sdma
276 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
281 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); in sdma_v5_0_init_microcode()
284 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); in sdma_v5_0_init_microcode()
287 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v5_0_init_microcode()
288 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); in sdma_v5_0_init_microcode()
289 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); in sdma_v5_0_init_microcode()
290 if (adev->sdma.instance[i].feature_version >= 20) in sdma_v5_0_init_microcode()
291 adev->sdma.instance[i].burst_nop = true; in sdma_v5_0_init_microcode()
298 info->fw = adev->sdma.instance[i].fw; in sdma_v5_0_init_microcode()
307 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
308 release_firmware(adev->sdma.instance[i].fw); in sdma_v5_0_init_microcode()
309 adev->sdma.instance[i].fw = NULL; in sdma_v5_0_init_microcode()
431 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_0_ring_insert_nop() local
435 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_insert_nop()
589 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; in sdma_v5_0_gfx_stop()
590 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; in sdma_v5_0_gfx_stop()
598 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_stop()
657 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_ctx_switch_enable()
699 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_enable()
727 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_resume()
728 ring = &adev->sdma.instance[i].ring; in sdma_v5_0_gfx_resume()
905 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_load_microcode()
906 if (!adev->sdma.instance[i].fw) in sdma_v5_0_load_microcode()
909 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v5_0_load_microcode()
914 (adev->sdma.instance[i].fw->data + in sdma_v5_0_load_microcode()
925 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); in sdma_v5_0_load_microcode()
1203 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_0_ring_pad_ib() local
1209 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_pad_ib()
1316 &adev->sdma.trap_irq); in sdma_v5_0_sw_init()
1323 &adev->sdma.trap_irq); in sdma_v5_0_sw_init()
1333 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_sw_init()
1334 ring = &adev->sdma.instance[i].ring; in sdma_v5_0_sw_init()
1346 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, in sdma_v5_0_sw_init()
1362 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_sw_fini()
1363 release_firmware(adev->sdma.instance[i].fw); in sdma_v5_0_sw_fini()
1364 adev->sdma.instance[i].fw = NULL; in sdma_v5_0_sw_fini()
1366 amdgpu_ring_fini(&adev->sdma.instance[i].ring); in sdma_v5_0_sw_fini()
1416 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_is_idle()
1527 amdgpu_fence_process(&adev->sdma.instance[0].ring); in sdma_v5_0_process_trap_irq()
1543 amdgpu_fence_process(&adev->sdma.instance[1].ring); in sdma_v5_0_process_trap_irq()
1573 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_update_medium_grain_clock_gating()
1610 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_update_medium_grain_light_sleep()
1737 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_set_ring_funcs()
1738 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; in sdma_v5_0_set_ring_funcs()
1739 adev->sdma.instance[i].ring.me = i; in sdma_v5_0_set_ring_funcs()
1754 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + in sdma_v5_0_set_irq_funcs()
1755 adev->sdma.num_instances; in sdma_v5_0_set_irq_funcs()
1756 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; in sdma_v5_0_set_irq_funcs()
1757 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; in sdma_v5_0_set_irq_funcs()
1826 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in sdma_v5_0_set_buffer_funcs()
1843 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_set_vm_pte_funcs()
1845 &adev->sdma.instance[i].ring.sched; in sdma_v5_0_set_vm_pte_funcs()
1847 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v5_0_set_vm_pte_funcs()