Lines Matching refs:sdma
49 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; in si_dma_ring_get_wptr()
57 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; in si_dma_ring_set_wptr()
120 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_stop()
121 ring = &adev->sdma.instance[i].ring; in si_dma_stop()
139 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_start()
140 ring = &adev->sdma.instance[i].ring; in si_dma_start()
475 adev->sdma.num_instances = 2; in si_dma_early_init()
493 &adev->sdma.trap_irq); in si_dma_sw_init()
499 &adev->sdma.trap_irq); in si_dma_sw_init()
503 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_sw_init()
504 ring = &adev->sdma.instance[i].ring; in si_dma_sw_init()
509 &adev->sdma.trap_irq, in si_dma_sw_init()
525 for (i = 0; i < adev->sdma.num_instances; i++) in si_dma_sw_fini()
526 amdgpu_ring_fini(&adev->sdma.instance[i].ring); in si_dma_sw_fini()
642 amdgpu_fence_process(&adev->sdma.instance[0].ring); in si_dma_process_trap_irq()
644 amdgpu_fence_process(&adev->sdma.instance[1].ring); in si_dma_process_trap_irq()
659 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_clockgating_state()
671 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_clockgating_state()
753 for (i = 0; i < adev->sdma.num_instances; i++) in si_dma_set_ring_funcs()
754 adev->sdma.instance[i].ring.funcs = &si_dma_ring_funcs; in si_dma_set_ring_funcs()
764 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; in si_dma_set_irq_funcs()
765 adev->sdma.trap_irq.funcs = &si_dma_trap_irq_funcs; in si_dma_set_irq_funcs()
831 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in si_dma_set_buffer_funcs()
847 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_vm_pte_funcs()
849 &adev->sdma.instance[i].ring.sched; in si_dma_set_vm_pte_funcs()
851 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()