Lines Matching refs:me
74 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); in uvd_v7_0_ring_get_rptr()
88 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_rptr()
89 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); in uvd_v7_0_enc_ring_get_rptr()
91 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); in uvd_v7_0_enc_ring_get_rptr()
105 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); in uvd_v7_0_ring_get_wptr()
122 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_wptr()
123 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); in uvd_v7_0_enc_ring_get_wptr()
125 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); in uvd_v7_0_enc_ring_get_wptr()
139 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
160 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_set_wptr()
161 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, in uvd_v7_0_enc_ring_set_wptr()
164 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, in uvd_v7_0_enc_ring_set_wptr()
446 sprintf(ring->name, "uvd_%d", ring->me); in uvd_v7_0_sw_init()
456 sprintf(ring->name, "uvd_enc_%d.%d", ring->me, i); in uvd_v7_0_sw_init()
1182 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_emit_fence()
1185 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence()
1188 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1191 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence()
1195 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence()
1198 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1201 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence()
1252 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v7_0_ring_test_ring()
1258 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_test_ring()
1262 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); in uvd_v7_0_ring_test_ring()
1289 if (!ring->me) in uvd_v7_0_ring_patch_cs_in_place()
1322 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); in uvd_v7_0_ring_emit_ib()
1326 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); in uvd_v7_0_ring_emit_ib()
1329 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); in uvd_v7_0_ring_emit_ib()
1332 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); in uvd_v7_0_ring_emit_ib()
1366 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_wreg()
1369 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_wreg()
1372 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_wreg()
1382 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_reg_wait()
1385 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_reg_wait()
1388 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); in uvd_v7_0_ring_emit_reg_wait()
1391 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_reg_wait()
1418 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); in uvd_v7_0_ring_insert_nop()
1488 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1494 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1497 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1506 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1518 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1520 srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1548 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1611 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1612 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1613 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1657 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1658 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1659 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1660 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1667 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1668 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1700 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1701 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1760 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1871 adev->uvd.inst[i].ring.me = i; in uvd_v7_0_set_ring_funcs()
1885 adev->uvd.inst[j].ring_enc[i].me = j; in uvd_v7_0_set_enc_ring_funcs()