Lines Matching refs:bitfields2
93 ib_packet->bitfields2.ib_base_lo = largep->u.low_part >> 2; in dbgdev_diq_submit_ib()
130 rm_packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT; in dbgdev_diq_submit_ib()
131 rm_packet->bitfields2.event_index = in dbgdev_diq_submit_ib()
134 rm_packet->bitfields2.cache_policy = cache_policy___release_mem__lru; in dbgdev_diq_submit_ib()
135 rm_packet->bitfields2.atc = 0; in dbgdev_diq_submit_ib()
136 rm_packet->bitfields2.tc_wb_action_ena = 1; in dbgdev_diq_submit_ib()
382 packets_vec[0].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET; in dbgdev_address_watch_diq()
383 packets_vec[0].bitfields2.insert_vmid = 1; in dbgdev_address_watch_diq()
385 packets_vec[1].bitfields2.insert_vmid = 0; in dbgdev_address_watch_diq()
387 packets_vec[2].bitfields2.insert_vmid = 0; in dbgdev_address_watch_diq()
389 packets_vec[3].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET; in dbgdev_address_watch_diq()
390 packets_vec[3].bitfields2.insert_vmid = 1; in dbgdev_address_watch_diq()
427 packets_vec[0].bitfields2.reg_offset = in dbgdev_address_watch_diq()
438 packets_vec[1].bitfields2.reg_offset = in dbgdev_address_watch_diq()
448 packets_vec[2].bitfields2.reg_offset = in dbgdev_address_watch_diq()
464 packets_vec[3].bitfields2.reg_offset = in dbgdev_address_watch_diq()
652 packets_vec[0].bitfields2.reg_offset = in dbgdev_wave_control_diq()
655 packets_vec[0].bitfields2.insert_vmid = 0; in dbgdev_wave_control_diq()
661 packets_vec[1].bitfields2.reg_offset = SQ_CMD / 4 - AMD_CONFIG_REG_BASE; in dbgdev_wave_control_diq()
663 packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET; in dbgdev_wave_control_diq()
664 packets_vec[1].bitfields2.insert_vmid = 1; in dbgdev_wave_control_diq()
676 packets_vec[2].bitfields2.reg_offset = in dbgdev_wave_control_diq()
679 packets_vec[2].bitfields2.insert_vmid = 0; in dbgdev_wave_control_diq()