Lines Matching refs:u32All
239 addrHi->u32All = 0; in dbgdev_address_watch_set_registers()
240 addrLo->u32All = 0; in dbgdev_address_watch_set_registers()
241 cntl->u32All = 0; in dbgdev_address_watch_set_registers()
260 cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT; in dbgdev_address_watch_set_registers()
286 addrHi.u32All = 0; in dbgdev_address_watch_nodiq()
287 addrLo.u32All = 0; in dbgdev_address_watch_nodiq()
288 cntl.u32All = 0; in dbgdev_address_watch_nodiq()
327 cntl.u32All, in dbgdev_address_watch_nodiq()
328 addrHi.u32All, in dbgdev_address_watch_nodiq()
329 addrLo.u32All); in dbgdev_address_watch_nodiq()
351 addrHi.u32All = 0; in dbgdev_address_watch_diq()
352 addrLo.u32All = 0; in dbgdev_address_watch_diq()
353 cntl.u32All = 0; in dbgdev_address_watch_diq()
430 packets_vec[0].reg_data[0] = cntl.u32All; in dbgdev_address_watch_diq()
440 packets_vec[1].reg_data[0] = addrHi.u32All; in dbgdev_address_watch_diq()
450 packets_vec[2].reg_data[0] = addrLo.u32All; in dbgdev_address_watch_diq()
466 packets_vec[3].reg_data[0] = cntl.u32All; in dbgdev_address_watch_diq()
495 reg_sq_cmd.u32All = 0; in dbgdev_wave_control_set_registers()
496 reg_gfx_index.u32All = 0; in dbgdev_wave_control_set_registers()
595 reg_sq_cmd.u32All = 0; in dbgdev_wave_control_diq()
656 packets_vec[0].reg_data[0] = reg_gfx_index.u32All; in dbgdev_wave_control_diq()
665 packets_vec[1].reg_data[0] = reg_sq_cmd.u32All; in dbgdev_wave_control_diq()
669 reg_gfx_index.u32All = 0; in dbgdev_wave_control_diq()
680 packets_vec[2].reg_data[0] = reg_gfx_index.u32All; in dbgdev_wave_control_diq()
705 reg_sq_cmd.u32All = 0; in dbgdev_wave_control_nodiq()
756 reg_gfx_index.u32All, in dbgdev_wave_control_nodiq()
757 reg_sq_cmd.u32All); in dbgdev_wave_control_nodiq()
772 reg_sq_cmd.u32All = 0; in dbgdev_wave_reset_wavefronts()
815 reg_gfx_index.u32All, in dbgdev_wave_reset_wavefronts()
816 reg_sq_cmd.u32All); in dbgdev_wave_reset_wavefronts()