Lines Matching refs:uint8_t
150 uint8_t TdpClampMode;
151 uint8_t TdcClampMode;
152 uint8_t ThermClampMode;
153 uint8_t VoltageBusy;
157 uint8_t LevelChangeInProgress;
158 uint8_t UpHyst;
160 uint8_t DownHyst;
161 uint8_t VoltageDownHyst;
162 uint8_t DpmEnable;
163 uint8_t DpmRunning;
165 uint8_t DpmForce;
166 uint8_t DpmForceLevel;
167 uint8_t DisplayWatermark;
168 uint8_t McArbIndex;
172 uint8_t AcpiReq;
173 uint8_t AcpiAck;
174 uint8_t GfxClkSlow;
175 uint8_t GpioClampMode;
177 uint8_t FpsFilterWeight;
178 uint8_t EnabledLevelsChange;
179 uint8_t DteClampMode;
180 uint8_t FpsClampMode;
185 void (*TargetStateCalculator)(uint8_t);
186 void (*SavedTargetStateCalculator)(uint8_t);
191 uint8_t FpsEnabled;
192 uint8_t MaxPerfLevel;
193 uint8_t AllowLowClkInterruptToHost;
194 uint8_t FpsRunning;
208 uint8_t HighestVidOffset;
209 uint8_t CurrentVidOffset;
211 uint8_t CurrentPhases;
212 uint8_t HighestPhases;
214 uint8_t AvsOffset;
215 uint8_t AvsOffsetApplied;
217 uint8_t ControllerBusy;
218 uint8_t CurrentVid;
221 uint8_t RequestedPhases[SMU7_MAX_VOLTAGE_CLIENTS];
223 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
224 uint8_t TargetIndex;
225 uint8_t Delay;
226 uint8_t ControllerEnable;
227 uint8_t ControllerRunning;
234 uint8_t CurrentVddciVid;
235 uint8_t TargetVddciIndex;
246 uint8_t DpmEnable;
247 uint8_t DpmRunning;
248 uint8_t DpmForce;
249 uint8_t DpmForceLevel;
251 uint8_t CurrentLinkSpeed;
252 uint8_t EnabledLevelsChange;
258 uint8_t DpmMode;
259 uint8_t AcpiReq;
260 uint8_t AcpiAck;
261 uint8_t CurrentLinkLevel;
318 uint8_t CalculationRepeats;
319 uint8_t WaterfallUp;
320 uint8_t WaterfallDown;
321 uint8_t WaterfallLimit;
334 uint8_t ControllerEnable;
335 uint8_t ControllerRunning;
336 uint8_t WaterfallUp;
337 uint8_t WaterfallDown;
338 uint8_t WaterfallLimit;
339 uint8_t padding[3];
381 uint8_t DisplayPhy1Config;
382 uint8_t DisplayPhy2Config;
383 uint8_t DisplayPhy3Config;
384 uint8_t DisplayPhy4Config;
386 uint8_t DisplayPhy5Config;
387 uint8_t DisplayPhy6Config;
388 uint8_t DisplayPhy7Config;
389 uint8_t DisplayPhy8Config;
395 uint8_t SClkDpmEnabledLevels;
396 uint8_t MClkDpmEnabledLevels;
397 uint8_t LClkDpmEnabledLevels;
398 uint8_t PCIeDpmEnabledLevels;
408 uint8_t DPMFreezeAndForced;
409 uint8_t Activity_Weight;
410 uint8_t Reserved8[2];
452 uint8_t waterfall_up;
453 uint8_t waterfall_down;
454 uint8_t pstate;
455 uint8_t clamp_mode;
489 uint8_t BlockId;
490 uint8_t SignalId;
491 uint8_t Threshold;
492 uint8_t Padding;