Lines Matching refs:uint8_t
54 uint8_t a_shift;
55 uint8_t b_shift;
56 uint8_t c_shift;
57 uint8_t x_shift;
82 uint8_t index;
197 uint8_t waterfall_up;
198 uint8_t waterfall_down;
199 uint8_t waterfall_limit;
200 uint8_t spare;
234 uint8_t TdpClampMode;
235 uint8_t TdcClampMode;
236 uint8_t ThermClampMode;
237 uint8_t VoltageBusy;
241 uint8_t LevelChangeInProgress;
242 uint8_t UpHyst;
244 uint8_t DownHyst;
245 uint8_t VoltageDownHyst;
246 uint8_t DpmEnable;
247 uint8_t DpmRunning;
249 uint8_t DpmForce;
250 uint8_t DpmForceLevel;
251 uint8_t DisplayWatermark;
252 uint8_t McArbIndex;
256 uint8_t AcpiReq;
257 uint8_t AcpiAck;
258 uint8_t GfxClkSlow;
259 uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */
261 uint8_t FpsFilterWeight;
262 uint8_t EnabledLevelsChange;
263 uint8_t DteClampMode;
264 uint8_t FpsClampMode;
269 void (*TargetStateCalculator)(uint8_t);
270 void (*SavedTargetStateCalculator)(uint8_t);
275 uint8_t FpsEnabled;
276 uint8_t MaxPerfLevel;
277 uint8_t AllowLowClkInterruptToHost;
278 uint8_t FpsRunning;
291 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
294 uint8_t Vddc;
295 uint8_t Vddci;
296 uint8_t VddGfx;
297 uint8_t Phases;
306 uint8_t HighestVidOffset;
307 uint8_t CurrentVidOffset;
309 uint8_t ControllerBusy;
310 uint8_t CurrentVid;
311 uint8_t CurrentVddciVid;
312 uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */
315 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
317 uint8_t TargetIndex;
318 uint8_t Delay;
319 uint8_t ControllerEnable;
320 uint8_t ControllerRunning;
323 uint8_t OverrideVoltage;
324 uint8_t VddcUseUlvOffset;
325 uint8_t VddGfxUseUlvOffset;
326 uint8_t padding;
336 uint8_t *VddcFollower1;
337 uint8_t *VddcFollower2;
348 uint8_t DpmEnable;
349 uint8_t DpmRunning;
350 uint8_t DpmForce;
351 uint8_t DpmForceLevel;
353 uint8_t CurrentLinkSpeed;
354 uint8_t EnabledLevelsChange;
360 uint8_t DpmMode;
361 uint8_t AcpiReq;
362 uint8_t AcpiAck;
363 uint8_t CurrentLinkLevel;
388 uint8_t SidOptionPower;
389 uint8_t SidOptionCurrent;
421 uint8_t ControllerEnable;
422 uint8_t ControllerRunning;
423 uint8_t AutoTmonCalInterval;
424 uint8_t AutoTmonCalEnable;
426 uint8_t ThermalDpmEnabled;
427 uint8_t SclkEnabledMask;
428 uint8_t spare[2];
476 uint8_t DisplayPhy1Config;
477 uint8_t DisplayPhy2Config;
478 uint8_t DisplayPhy3Config;
479 uint8_t DisplayPhy4Config;
481 uint8_t DisplayPhy5Config;
482 uint8_t DisplayPhy6Config;
483 uint8_t DisplayPhy7Config;
484 uint8_t DisplayPhy8Config;
490 uint8_t SClkDpmEnabledLevels;
491 uint8_t MClkDpmEnabledLevels;
492 uint8_t LClkDpmEnabledLevels;
493 uint8_t PCIeDpmEnabledLevels;
495 uint8_t UVDDpmEnabledLevels;
496 uint8_t SAMUDpmEnabledLevels;
497 uint8_t ACPDpmEnabledLevels;
498 uint8_t VCEDpmEnabledLevels;
564 uint8_t BlockId;
565 uint8_t SignalId;
566 uint8_t Threshold;
567 uint8_t Padding;
659 uint8_t minVID;
660 uint8_t maxVID;
675 uint8_t setting;
676 uint8_t padding[3];