Lines Matching refs:vddc
1846 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_and_t_formula() local
1851 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_and_t_formula()
1860 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; in si_calculate_leakage_for_v_and_t_formula()
1863 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); in si_calculate_leakage_for_v_and_t_formula()
1865 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_and_t_formula()
1884 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_formula() local
1887 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_formula()
1891 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); in si_calculate_leakage_for_v_formula()
1893 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_formula()
2372 SISLANDS_SMC_VOLTAGE_VALUE vddc; in si_populate_power_containment_values() local
2428 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2432 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc); in si_populate_power_containment_values()
2437 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2441 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc); in si_populate_power_containment_values()
2628 if (table->entries[i].vddc > *max) in si_get_cac_std_voltage_max_min()
2629 *max = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2630 if (table->entries[i].vddc < *min) in si_get_cac_std_voltage_max_min()
2631 *min = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
3296 u16 *vddc, u16 *vddci) in btc_apply_voltage_delta_rules() argument
3301 if ((0 == *vddc) || (0 == *vddci)) in btc_apply_voltage_delta_rules()
3304 if (*vddc > *vddci) { in btc_apply_voltage_delta_rules()
3305 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
3307 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
3311 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
3314 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc; in btc_apply_voltage_delta_rules()
3382 u16 vddc; in rv770_get_max_vddc() local
3384 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc)) in rv770_get_max_vddc()
3387 pi->max_vddc = vddc; in rv770_get_max_vddc()
3415 u16 vddc, vddci, min_vce_voltage = 0; in si_apply_state_adjust_rules() local
3470 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
3471 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
3479 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3480 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3529 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3532 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3545 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3556 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3562 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3563 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3591 if (ps->performance_levels[i].vddc < min_vce_voltage) in si_apply_state_adjust_rules()
3592 ps->performance_levels[i].vddc = min_vce_voltage; in si_apply_state_adjust_rules()
3595 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3601 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3604 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3609 max_limits->vddc, max_limits->vddci, in si_apply_state_adjust_rules()
3610 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3616 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3674 u16 vddc, count = 0; in si_get_leakage_vddc() local
3678 …ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 +… in si_get_leakage_vddc()
3680 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { in si_get_leakage_vddc()
3681 si_pi->leakage_voltage.entries[count].voltage = vddc; in si_get_leakage_vddc()
4608 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4611 …>pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4623 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4626 …>pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4633 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4864 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4865 &table->initialState.level.vddc); in si_populate_smc_initial_state()
4871 &table->initialState.level.vddc, in si_populate_smc_initial_state()
4875 table->initialState.level.vddc.index, in si_populate_smc_initial_state()
4888 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4891 &table->initialState.level.vddc); in si_populate_smc_initial_state()
4956 pi->acpi_vddc, &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4961 &table->ACPIState.level.vddc, &std_vddc); in si_populate_smc_acpi_state()
4964 table->ACPIState.level.vddc.index, in si_populate_smc_acpi_state()
4975 &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4979 pi->min_vddc_in_table, &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4984 &table->ACPIState.level.vddc, &std_vddc); in si_populate_smc_acpi_state()
4988 table->ACPIState.level.vddc.index, in si_populate_smc_acpi_state()
5003 &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
5094 state->level.std_vddc = state->level.vddc; in si_populate_ulv_state()
5202 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
5490 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
5495 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
5500 level->vddc.index, &level->std_vddc); in si_convert_power_level_to_smc()
5514 pl->vddc, in si_convert_power_level_to_smc()
5517 &level->vddc); in si_convert_power_level_to_smc()
5606 if (ulv->pl.vddc < in si_is_state_ulv_compatible()
5739 if (ulv->supported && ulv->pl.vddc) { in si_upload_ulv_state()
6106 if (ulv->supported && ulv->pl.vddc != 0) in si_populate_mc_reg_table()
7148 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); in si_parse_pplib_clock_info()
7157 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, in si_parse_pplib_clock_info()
7160 pl->vddc = leakage_voltage; in si_parse_pplib_clock_info()
7163 pi->acpi_vddc = pl->vddc; in si_parse_pplib_clock_info()
7179 if (pi->min_vddc_in_table > pl->vddc) in si_parse_pplib_clock_info()
7180 pi->min_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
7182 if (pi->max_vddc_in_table < pl->vddc) in si_parse_pplib_clock_info()
7183 pi->max_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
7187 u16 vddc, vddci, mvdd; in si_parse_pplib_clock_info() local
7188 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd); in si_parse_pplib_clock_info()
7191 pl->vddc = vddc; in si_parse_pplib_clock_info()
7200 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
7497 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()
7907 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_print_power_state()
7910 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); in si_dpm_print_power_state()
7932 (si_cpl1->vddc == si_cpl2->vddc) && in si_are_power_levels_equal()