Lines Matching refs:dcrtc
82 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs) in armada_drm_crtc_update_regs() argument
85 void __iomem *reg = dcrtc->base + regs->offset; in armada_drm_crtc_update_regs()
96 static void armada_drm_crtc_update(struct armada_crtc *dcrtc, bool enable) in armada_drm_crtc_update() argument
100 dumb_ctrl = dcrtc->cfg_dumb_ctrl; in armada_drm_crtc_update()
118 dcrtc->base + LCD_SPU_DUMB_CTRL); in armada_drm_crtc_update()
123 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_queue_state_event() local
130 dcrtc->event = event; in armada_drm_crtc_queue_state_event()
175 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_mode_valid() local
187 if (!dcrtc->variant->has_spu_adv_reg && in armada_drm_crtc_mode_valid()
202 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_mode_fixup() local
220 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL); in armada_drm_crtc_mode_fixup()
228 static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask) in armada_drm_crtc_disable_irq() argument
230 if (dcrtc->irq_ena & mask) { in armada_drm_crtc_disable_irq()
231 dcrtc->irq_ena &= ~mask; in armada_drm_crtc_disable_irq()
232 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_disable_irq()
236 static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask) in armada_drm_crtc_enable_irq() argument
238 if ((dcrtc->irq_ena & mask) != mask) { in armada_drm_crtc_enable_irq()
239 dcrtc->irq_ena |= mask; in armada_drm_crtc_enable_irq()
240 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_enable_irq()
241 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) in armada_drm_crtc_enable_irq()
242 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_crtc_enable_irq()
246 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) in armada_drm_crtc_irq() argument
249 void __iomem *base = dcrtc->base; in armada_drm_crtc_irq()
252 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); in armada_drm_crtc_irq()
254 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num); in armada_drm_crtc_irq()
257 drm_crtc_handle_vblank(&dcrtc->crtc); in armada_drm_crtc_irq()
259 spin_lock(&dcrtc->irq_lock); in armada_drm_crtc_irq()
260 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { in armada_drm_crtc_irq()
264 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); in armada_drm_crtc_irq()
265 writel_relaxed(dcrtc->v[i].spu_v_h_total, in armada_drm_crtc_irq()
270 val |= dcrtc->v[i].spu_adv_reg; in armada_drm_crtc_irq()
274 if (stat & dcrtc->irq_ena & DUMB_FRAMEDONE) { in armada_drm_crtc_irq()
275 if (dcrtc->update_pending) { in armada_drm_crtc_irq()
276 armada_drm_crtc_update_regs(dcrtc, dcrtc->regs); in armada_drm_crtc_irq()
277 dcrtc->update_pending = false; in armada_drm_crtc_irq()
279 if (dcrtc->cursor_update) { in armada_drm_crtc_irq()
280 writel_relaxed(dcrtc->cursor_hw_pos, in armada_drm_crtc_irq()
282 writel_relaxed(dcrtc->cursor_hw_sz, in armada_drm_crtc_irq()
288 dcrtc->cursor_update = false; in armada_drm_crtc_irq()
290 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); in armada_drm_crtc_irq()
292 spin_unlock(&dcrtc->irq_lock); in armada_drm_crtc_irq()
294 if (stat & VSYNC_IRQ && !dcrtc->update_pending) { in armada_drm_crtc_irq()
295 event = xchg(&dcrtc->event, NULL); in armada_drm_crtc_irq()
297 spin_lock(&dcrtc->crtc.dev->event_lock); in armada_drm_crtc_irq()
298 drm_crtc_send_vblank_event(&dcrtc->crtc, event); in armada_drm_crtc_irq()
299 spin_unlock(&dcrtc->crtc.dev->event_lock); in armada_drm_crtc_irq()
300 drm_crtc_vblank_put(&dcrtc->crtc); in armada_drm_crtc_irq()
307 struct armada_crtc *dcrtc = arg; in armada_drm_irq() local
308 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_irq()
315 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_irq()
317 trace_armada_drm_irq(&dcrtc->crtc, stat); in armada_drm_irq()
320 v = stat & dcrtc->irq_ena; in armada_drm_irq()
323 armada_drm_crtc_irq(dcrtc, stat); in armada_drm_irq()
333 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_mode_set_nofb() local
351 dcrtc->variant->compute_clock(dcrtc, adj, &sclk); in armada_drm_crtc_mode_set_nofb()
355 spin_lock_irqsave(&dcrtc->irq_lock, flags); in armada_drm_crtc_mode_set_nofb()
357 dcrtc->interlaced = interlaced; in armada_drm_crtc_mode_set_nofb()
359 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | in armada_drm_crtc_mode_set_nofb()
361 dcrtc->v[1].spu_v_porch = tm << 16 | bm; in armada_drm_crtc_mode_set_nofb()
363 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN; in armada_drm_crtc_mode_set_nofb()
368 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN; in armada_drm_crtc_mode_set_nofb()
369 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total + in armada_drm_crtc_mode_set_nofb()
371 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1; in armada_drm_crtc_mode_set_nofb()
373 dcrtc->v[0] = dcrtc->v[1]; in armada_drm_crtc_mode_set_nofb()
380 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); in armada_drm_crtc_mode_set_nofb()
381 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, in armada_drm_crtc_mode_set_nofb()
384 if (dcrtc->variant->has_spu_adv_reg) in armada_drm_crtc_mode_set_nofb()
385 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, in armada_drm_crtc_mode_set_nofb()
411 armada_drm_crtc_update_regs(dcrtc, regs); in armada_drm_crtc_mode_set_nofb()
412 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); in armada_drm_crtc_mode_set_nofb()
436 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_atomic_begin() local
443 dcrtc->regs_idx = 0; in armada_drm_crtc_atomic_begin()
444 dcrtc->regs = dcrtc->atomic_regs; in armada_drm_crtc_atomic_begin()
452 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_atomic_flush() local
456 armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx); in armada_drm_crtc_atomic_flush()
463 dcrtc->update_pending = true; in armada_drm_crtc_atomic_flush()
465 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_atomic_flush()
466 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); in armada_drm_crtc_atomic_flush()
467 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_atomic_flush()
469 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_atomic_flush()
470 armada_drm_crtc_update_regs(dcrtc, dcrtc->regs); in armada_drm_crtc_atomic_flush()
471 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_atomic_flush()
480 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_atomic_disable() local
489 armada_drm_crtc_update(dcrtc, false); in armada_drm_crtc_atomic_disable()
496 if (dcrtc->variant->disable) in armada_drm_crtc_atomic_disable()
497 dcrtc->variant->disable(dcrtc); in armada_drm_crtc_atomic_disable()
518 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_atomic_enable() local
528 if (dcrtc->variant->enable) in armada_drm_crtc_atomic_enable()
529 dcrtc->variant->enable(dcrtc, &crtc->state->adjusted_mode); in armada_drm_crtc_atomic_enable()
531 armada_drm_crtc_update(dcrtc, true); in armada_drm_crtc_atomic_enable()
602 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload) in armada_drm_crtc_cursor_update() argument
604 uint32_t xoff, xscr, w = dcrtc->cursor_w, s; in armada_drm_crtc_cursor_update()
605 uint32_t yoff, yscr, h = dcrtc->cursor_h; in armada_drm_crtc_cursor_update()
612 if (dcrtc->cursor_x < 0) { in armada_drm_crtc_cursor_update()
613 xoff = -dcrtc->cursor_x; in armada_drm_crtc_cursor_update()
616 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) { in armada_drm_crtc_cursor_update()
618 xscr = dcrtc->cursor_x; in armada_drm_crtc_cursor_update()
619 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0); in armada_drm_crtc_cursor_update()
622 xscr = dcrtc->cursor_x; in armada_drm_crtc_cursor_update()
625 if (dcrtc->cursor_y < 0) { in armada_drm_crtc_cursor_update()
626 yoff = -dcrtc->cursor_y; in armada_drm_crtc_cursor_update()
629 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) { in armada_drm_crtc_cursor_update()
631 yscr = dcrtc->cursor_y; in armada_drm_crtc_cursor_update()
632 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0); in armada_drm_crtc_cursor_update()
635 yscr = dcrtc->cursor_y; in armada_drm_crtc_cursor_update()
639 s = dcrtc->cursor_w; in armada_drm_crtc_cursor_update()
640 if (dcrtc->interlaced) { in armada_drm_crtc_cursor_update()
646 if (!dcrtc->cursor_obj || !h || !w) { in armada_drm_crtc_cursor_update()
647 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
648 dcrtc->cursor_update = false; in armada_drm_crtc_cursor_update()
649 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); in armada_drm_crtc_cursor_update()
650 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
654 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
655 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_cursor_update()
657 dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_cursor_update()
658 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
665 armada_drm_crtc_cursor_tran(dcrtc->base); in armada_drm_crtc_cursor_update()
669 if (dcrtc->cursor_hw_sz != (h << 16 | w)) { in armada_drm_crtc_cursor_update()
670 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
671 dcrtc->cursor_update = false; in armada_drm_crtc_cursor_update()
672 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); in armada_drm_crtc_cursor_update()
673 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
677 struct armada_gem_object *obj = dcrtc->cursor_obj; in armada_drm_crtc_cursor_update()
682 armada_load_cursor_argb(dcrtc->base, pix, s, w, h); in armada_drm_crtc_cursor_update()
686 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
687 dcrtc->cursor_hw_pos = yscr << 16 | xscr; in armada_drm_crtc_cursor_update()
688 dcrtc->cursor_hw_sz = h << 16 | w; in armada_drm_crtc_cursor_update()
689 dcrtc->cursor_update = true; in armada_drm_crtc_cursor_update()
690 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); in armada_drm_crtc_cursor_update()
691 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
704 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_cursor_set() local
709 if (!dcrtc->variant->has_spu_adv_reg) in armada_drm_crtc_cursor_set()
734 if (dcrtc->cursor_obj) { in armada_drm_crtc_cursor_set()
735 dcrtc->cursor_obj->update = NULL; in armada_drm_crtc_cursor_set()
736 dcrtc->cursor_obj->update_data = NULL; in armada_drm_crtc_cursor_set()
737 drm_gem_object_put(&dcrtc->cursor_obj->obj); in armada_drm_crtc_cursor_set()
739 dcrtc->cursor_obj = obj; in armada_drm_crtc_cursor_set()
740 dcrtc->cursor_w = w; in armada_drm_crtc_cursor_set()
741 dcrtc->cursor_h = h; in armada_drm_crtc_cursor_set()
742 ret = armada_drm_crtc_cursor_update(dcrtc, true); in armada_drm_crtc_cursor_set()
744 obj->update_data = dcrtc; in armada_drm_crtc_cursor_set()
753 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_cursor_move() local
757 if (!dcrtc->variant->has_spu_adv_reg) in armada_drm_crtc_cursor_move()
760 dcrtc->cursor_x = x; in armada_drm_crtc_cursor_move()
761 dcrtc->cursor_y = y; in armada_drm_crtc_cursor_move()
762 ret = armada_drm_crtc_cursor_update(dcrtc, false); in armada_drm_crtc_cursor_move()
769 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_destroy() local
772 if (dcrtc->cursor_obj) in armada_drm_crtc_destroy()
773 drm_gem_object_put(&dcrtc->cursor_obj->obj); in armada_drm_crtc_destroy()
775 priv->dcrtc[dcrtc->num] = NULL; in armada_drm_crtc_destroy()
776 drm_crtc_cleanup(&dcrtc->crtc); in armada_drm_crtc_destroy()
778 if (dcrtc->variant->disable) in armada_drm_crtc_destroy()
779 dcrtc->variant->disable(dcrtc); in armada_drm_crtc_destroy()
781 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_destroy()
783 of_node_put(dcrtc->crtc.port); in armada_drm_crtc_destroy()
785 kfree(dcrtc); in armada_drm_crtc_destroy()
799 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_enable_vblank() local
802 spin_lock_irqsave(&dcrtc->irq_lock, flags); in armada_drm_crtc_enable_vblank()
803 armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA); in armada_drm_crtc_enable_vblank()
804 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); in armada_drm_crtc_enable_vblank()
810 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_disable_vblank() local
813 spin_lock_irqsave(&dcrtc->irq_lock, flags); in armada_drm_crtc_disable_vblank()
814 armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA); in armada_drm_crtc_disable_vblank()
815 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); in armada_drm_crtc_disable_vblank()
832 int armada_crtc_select_clock(struct armada_crtc *dcrtc, in armada_crtc_select_clock() argument
848 dcrtc->crtc.base.id, dcrtc->crtc.name, desired_hz); in armada_crtc_select_clock()
879 dcrtc->crtc.base.id, dcrtc->crtc.name, in armada_crtc_select_clock()
899 dcrtc->crtc.base.id, dcrtc->crtc.name, in armada_crtc_select_clock()
914 struct armada_crtc *dcrtc; in armada_drm_crtc_create() local
923 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL); in armada_drm_crtc_create()
924 if (!dcrtc) { in armada_drm_crtc_create()
930 dev_set_drvdata(dev, dcrtc); in armada_drm_crtc_create()
932 dcrtc->variant = variant; in armada_drm_crtc_create()
933 dcrtc->base = base; in armada_drm_crtc_create()
934 dcrtc->num = drm->mode_config.num_crtc; in armada_drm_crtc_create()
935 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0; in armada_drm_crtc_create()
936 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; in armada_drm_crtc_create()
937 spin_lock_init(&dcrtc->irq_lock); in armada_drm_crtc_create()
938 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; in armada_drm_crtc_create()
941 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); in armada_drm_crtc_create()
942 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); in armada_drm_crtc_create()
943 writel_relaxed(dcrtc->spu_iopad_ctrl, in armada_drm_crtc_create()
944 dcrtc->base + LCD_SPU_IOPAD_CONTROL); in armada_drm_crtc_create()
945 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); in armada_drm_crtc_create()
948 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_create()
949 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); in armada_drm_crtc_create()
950 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_create()
951 readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_crtc_create()
952 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_crtc_create()
955 dcrtc); in armada_drm_crtc_create()
959 if (dcrtc->variant->init) { in armada_drm_crtc_create()
960 ret = dcrtc->variant->init(dcrtc, dev); in armada_drm_crtc_create()
966 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); in armada_drm_crtc_create()
968 priv->dcrtc[dcrtc->num] = dcrtc; in armada_drm_crtc_create()
970 dcrtc->crtc.port = port; in armada_drm_crtc_create()
984 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, primary, NULL, in armada_drm_crtc_create()
989 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); in armada_drm_crtc_create()
991 ret = drm_mode_crtc_set_gamma_size(&dcrtc->crtc, 256); in armada_drm_crtc_create()
995 drm_crtc_enable_color_mgmt(&dcrtc->crtc, 0, false, 256); in armada_drm_crtc_create()
997 return armada_overlay_plane_create(drm, 1 << dcrtc->num); in armada_drm_crtc_create()
1002 kfree(dcrtc); in armada_drm_crtc_create()
1055 struct armada_crtc *dcrtc = dev_get_drvdata(dev); in armada_lcd_unbind() local
1057 armada_drm_crtc_destroy(&dcrtc->crtc); in armada_lcd_unbind()