Lines Matching refs:REG_READ
133 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
145 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
151 *val = REG_READ(SB_DATA); in cdv_sb_read()
168 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
181 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
202 REG_READ(DPIO_CFG); in cdv_sb_reset()
471 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
474 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
475 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
483 REG_READ(OV_OVADD); in cdv_disable_sr()
499 fw = REG_READ(DSPFW1); in cdv_update_wm()
506 fw = REG_READ(DSPFW2); in cdv_update_wm()
535 REG_READ(FW_BLC_SELF); in cdv_update_wm()
562 pfit_control = REG_READ(PFIT_CONTROL); in cdv_intel_panel_fitter_pipe()
678 pipeconf = REG_READ(map->conf); in cdv_intel_crtc_mode_set()
698 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) in cdv_intel_crtc_mode_set()
717 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
729 u32 lvds = REG_READ(LVDS); in cdv_intel_crtc_mode_set()
749 REG_READ(LVDS); in cdv_intel_crtc_mode_set()
762 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
763 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
767 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
798 REG_READ(map->conf); in cdv_intel_crtc_mode_set()
843 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
845 fp = REG_READ(map->fp0); in cdv_intel_crtc_clock_get()
847 fp = REG_READ(map->fp1); in cdv_intel_crtc_clock_get()
848 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in cdv_intel_crtc_clock_get()
923 htot = REG_READ(map->htotal); in cdv_intel_crtc_mode_get()
924 hsync = REG_READ(map->hsync); in cdv_intel_crtc_mode_get()
925 vtot = REG_READ(map->vtotal); in cdv_intel_crtc_mode_get()
926 vsync = REG_READ(map->vsync); in cdv_intel_crtc_mode_get()