Lines Matching refs:REG_WRITE
208 REG_WRITE(PFIT_CONTROL, 0); in psb_intel_crtc_mode_set()
213 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
214 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
244 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
248 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
249 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
255 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
261 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in psb_intel_crtc_mode_set()
263 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in psb_intel_crtc_mode_set()
265 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in psb_intel_crtc_mode_set()
267 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in psb_intel_crtc_mode_set()
269 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in psb_intel_crtc_mode_set()
271 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in psb_intel_crtc_mode_set()
276 REG_WRITE(map->size, in psb_intel_crtc_mode_set()
278 REG_WRITE(map->pos, 0); in psb_intel_crtc_mode_set()
279 REG_WRITE(map->src, in psb_intel_crtc_mode_set()
281 REG_WRITE(map->conf, pipeconf); in psb_intel_crtc_mode_set()
286 REG_WRITE(map->cntr, dspcntr); in psb_intel_crtc_mode_set()
477 REG_WRITE(control[gma_crtc->pipe], 0); in psb_intel_cursor_init()
478 REG_WRITE(base[gma_crtc->pipe], 0); in psb_intel_cursor_init()