Lines Matching refs:i9xx_plane
123 enum i9xx_plane_id i9xx_plane) in i9xx_plane_has_fbc() argument
129 return i9xx_plane == PLANE_A; /* tied to pipe A */ in i9xx_plane_has_fbc()
131 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || in i9xx_plane_has_fbc()
132 i9xx_plane == PLANE_C; in i9xx_plane_has_fbc()
134 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; in i9xx_plane_has_fbc()
136 return i9xx_plane == PLANE_A; in i9xx_plane_has_fbc()
142 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_has_windowing() local
145 return i9xx_plane == PLANE_B; in i9xx_plane_has_windowing()
149 return i9xx_plane == PLANE_C; in i9xx_plane_has_windowing()
151 return i9xx_plane == PLANE_B || in i9xx_plane_has_windowing()
152 i9xx_plane == PLANE_C; in i9xx_plane_has_windowing()
426 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_update_plane() local
449 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), in i9xx_update_plane()
458 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), in i9xx_update_plane()
460 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), in i9xx_update_plane()
462 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { in i9xx_update_plane()
463 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), in i9xx_update_plane()
465 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), in i9xx_update_plane()
467 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); in i9xx_update_plane()
471 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), in i9xx_update_plane()
474 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), in i9xx_update_plane()
476 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), in i9xx_update_plane()
485 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_update_plane()
487 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i9xx_update_plane()
490 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), in i9xx_update_plane()
500 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_disable_plane() local
518 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_disable_plane()
520 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); in i9xx_disable_plane()
522 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); in i9xx_disable_plane()
536 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in g4x_primary_async_flip() local
543 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in g4x_primary_async_flip()
544 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in g4x_primary_async_flip()
557 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in vlv_primary_async_flip() local
561 intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), in vlv_primary_async_flip()
594 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); in ivb_primary_enable_flip_done()
604 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); in ivb_primary_disable_flip_done()
614 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); in ilk_primary_enable_flip_done()
624 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); in ilk_primary_disable_flip_done()
655 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_get_hw_state() local
670 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()
740 if (plane->i9xx_plane == PLANE_C) in i9xx_plane_max_stride()
786 plane->i9xx_plane = (enum i9xx_plane_id) !pipe; in intel_primary_plane_create()
788 plane->i9xx_plane = (enum i9xx_plane_id) pipe; in intel_primary_plane_create()
792 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane); in intel_primary_plane_create()
892 plane_name(plane->i9xx_plane)); in intel_primary_plane_create()
965 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_get_initial_plane_config() local
988 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()
1009 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); in i9xx_get_initial_plane_config()
1010 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
1014 DSPTILEOFF(i9xx_plane)); in i9xx_get_initial_plane_config()
1017 DSPLINOFF(i9xx_plane)); in i9xx_get_initial_plane_config()
1018 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
1020 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)); in i9xx_get_initial_plane_config()
1028 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)); in i9xx_get_initial_plane_config()