Lines Matching refs:tc_port
1156 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in icl_mg_phy_set_signal_levels() local
1171 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1173 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1175 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1177 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1182 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1186 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1188 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1192 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1197 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1205 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1207 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1215 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1226 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1231 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1236 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1244 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1246 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1254 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1260 MG_TX1_PISO_READLOAD(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1262 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), in icl_mg_phy_set_signal_levels()
1266 MG_TX2_PISO_READLOAD(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1268 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), in icl_mg_phy_set_signal_levels()
1277 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in tgl_dkl_phy_set_signal_levels() local
1298 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), in tgl_dkl_phy_set_signal_levels()
1299 HIP_INDEX_VAL(tc_port, ln)); in tgl_dkl_phy_set_signal_levels()
1301 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); in tgl_dkl_phy_set_signal_levels()
1304 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); in tgl_dkl_phy_set_signal_levels()
1307 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); in tgl_dkl_phy_set_signal_levels()
1309 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); in tgl_dkl_phy_set_signal_levels()
1312 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); in tgl_dkl_phy_set_signal_levels()
1314 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); in tgl_dkl_phy_set_signal_levels()
1316 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); in tgl_dkl_phy_set_signal_levels()
1696 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_enable_clock() local
1708 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); in icl_ddi_tc_enable_clock()
1716 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_disable_clock() local
1722 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); in icl_ddi_tc_disable_clock()
1732 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_is_clock_enabled() local
1743 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); in icl_ddi_tc_is_clock_enabled()
1749 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_get_pll() local
1764 id = icl_tc_port_to_pll_id(tc_port); in icl_ddi_tc_get_pll()
2015 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); in icl_program_mg_dp_mode() local
2025 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), in icl_program_mg_dp_mode()
2026 HIP_INDEX_VAL(tc_port, 0x0)); in icl_program_mg_dp_mode()
2027 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); in icl_program_mg_dp_mode()
2028 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), in icl_program_mg_dp_mode()
2029 HIP_INDEX_VAL(tc_port, 0x1)); in icl_program_mg_dp_mode()
2030 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); in icl_program_mg_dp_mode()
2032 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); in icl_program_mg_dp_mode()
2033 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); in icl_program_mg_dp_mode()
2091 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), in icl_program_mg_dp_mode()
2092 HIP_INDEX_VAL(tc_port, 0x0)); in icl_program_mg_dp_mode()
2093 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); in icl_program_mg_dp_mode()
2094 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), in icl_program_mg_dp_mode()
2095 HIP_INDEX_VAL(tc_port, 0x1)); in icl_program_mg_dp_mode()
2096 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); in icl_program_mg_dp_mode()
2098 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); in icl_program_mg_dp_mode()
2099 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); in icl_program_mg_dp_mode()
4373 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') argument
4440 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); in intel_ddi_init() local
4447 tc_port != TC_PORT_NONE ? "TC" : "", in intel_ddi_init()
4448 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); in intel_ddi_init()
4450 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); in intel_ddi_init() local
4457 tc_port != TC_PORT_NONE ? "TC" : "", in intel_ddi_init()
4458 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); in intel_ddi_init()